Texas Instruments

Makes analog and embedded chips in its own plants

Layout Engineer

Silicon & ASIC DesignConfirmed live in the last 24 hours

Full-timeBengaluru, Karnataka, IndiaNo salary listedIn-person

About the Job

Requirements

Full-chip layout experience from definition through release of an integrated circuit to production.
Strong layout-versus-schematic, design-rule-check, electrical-rule-check, and antenna-debug skills.
Proficiency in analog and mixed-signal layout techniques and verification processes, including device matching, power-bus design, cross-talk avoidance, and electrostatic-discharge/latch-up protection techniques.
Good understanding of layout parasitics, including resistance, capacitance, diodes, and bipolar junction transistors.
Good understanding of device physics and semiconductor fabrication processes.
Experience with at least some of the listed technologies: 40 nm, 65 nm, 90 nm, 130 nm, 180 nm, BiCMOS, or BCD.
Proficiency with tools such as Virtuoso XL, Assura, PVS, or Voltas.
Ability to ramp up quickly on new tools and processes and mentor layout engineers.
Excellent teamwork, communication, problem-solving, and documentation skills.
Strong time-management skills for on-time project delivery.
Ability to take initiative and drive results.

Responsibilities

Frame the layout schedule, estimate effort, and develop risk and mitigation plans for layout activities for all layout engineers on the project.
Work closely with designers to understand the architecture and key requirements for the integrated circuit.
Balance area, performance, and schedule during layout development by collaborating with design, packaging, and process teams.
Work with the process development team to carry out PDK, P-cell, and design-rule updates.
Work with packaging engineers to develop custom lead frames for various packages.
Analyze and close electro-migration, thermal-gradient, electrostatic-discharge/latch-up performance, and layout-parasitic issues.
Routinely develop test vehicles for new process and package technology development.
Mentor and guide junior layout engineers and contract engineers, review their work, and provide feedback to meet quality and schedule standards.
Ensure the final layout meets design expectations and the layout checklist.
Identify needed process, quality, and cycle-time improvements and take necessary initiatives.

Desired Qualifications

Experience in automation or SKILL coding to reduce cycle time or perform quality checks.

Roles and responsibilities:

Frame the layout schedule, effort estimation, risk and mitigation plan of layout activities for all layout engineers in the project
Work closely with designers to understand the architecture and key requirements for the IC
Strike right balance of area, performance and schedule during layout development by collaborating with design, packaging and process teams
Work closely with Process development team to carry out PDK, P-cell and Design rule updates
Work closely with Packaging engineer to develop custom lead-frames for various packages
Analysis and closure of Electro Migration, Thermal gradients, ESD/LU performance and layout parasitic
Routinely develop test vehicles for new process & package technology development
Mentor and guide junior layout engineers/contract engineers, review their work and provide feedback to meet the quality and schedule norms
Responsible for the final layout which meets the design expectations and layout checklist.
Identify improvements needed in process/ quality/ cycle time and take up necessary initiatives

Knowledge and skills:

Full chip layout experience from definition through release of IC to production
Strong LVS, DRC, ERC, and antenna debug skills
Proficient in analog and mixed-signal layout techniques and verification process including Device Matching, Power Bus design, avoiding Cross-talk, ESD/LU protection techniques
Good understanding about all layout parasitics (R, C, diodes, BJTs)
Good understanding of device physics and semiconductor fabrication process
Must have worked on some of the Technologies like: 40nm, 65nm, 90nm, 130nm, 180nm, BiCMOS, BCD
Should be well versed with tools such as Virtuoso XL/Assura /PVS/Voltas
Ability to quickly ramp up on new tools/ process and mentor LEs
Experience in automation/ SKILL coding for reducing cycle time/ quality checks will be an added advantage
Requires excellent teamwork, good communication, strong problem-solving and documentation skills.
Strong time management skills for on-time project delivery
Ability to take initiatives and drive for results

About the Company

Texas Instruments

Makes analog and embedded chips in its own plants

Texas Instruments designs and makes analog and embedded processing chips, the basic parts inside cars, factory equipment, data centers, and consumer electronics, and it sells one of the broadest chip catalogs in the industry. In 1958, its engineer Jack Kilby built the first integrated circuit, the building block of modern electronics, and later won a Nobel Prize for it. Its analog chips regulate power and convert signals such as sound and heat into data, while its microcontrollers act as small built-in computers, and TI earns money selling both to device makers. It also makes the graphing calculators many students use in math class. Texas Instruments was founded in 1930 and is based in Dallas, Texas.

Company size: 10,001+
Company stage: IPO
Headquarters: Dallas, TX
Founded: 1930

Recently Posted Jobs

Explore more opportunities at Texas Instruments

See more jobs