Tesla

Makes electric cars, robotaxis and grid batteries

ASIC SOC Methodology Design Engineer - SI Hardware

Hardware Validation & TestingConfirmed live in the last 24 hours

Full-timeAustin, TX, USANo salary listedIn-person

About the Job

Requirements

A degree in Electrical Engineering, Computer Engineering, or equivalent experience is required.
At least 2 years of industry experience, including internships, working with digital design electronic design automation tools.
Hands-on experience with one or more of Spyglass (clock domain crossing, lint, or reset domain crossing), Conformal LEC, Formality, or an equivalent tool.
Understanding of clock domain crossings, reset synchronization, and synthesis fundamentals.
Proficiency in TCL and/or Python scripting.
Familiarity with SDC constraint development.
Elementary understanding of DFx/DFT scan modes and their impact on clock domain crossings and constraints.
Experience with both Synopsys and Cadence electronic design automation tool ecosystems.
Exposure to RTL filelist management and build systems at system-on-chip scale.
Experience with physical design flows, including synthesis, place and route, and timing analysis.

Responsibilities

Develop and own the electronic design automation methodology flows that enable system-on-chip design sign-off, spanning RTL integration, static verification, formal equivalence checking, and timing constraint development across a large multi-block system-on-chip.
Own RTL-to-physical-design integration and Spyglass lint sign-off flow, including filelist methodology, violation triage, and waiver creation.
Set up, run, and maintain Spyglass clock domain crossing sign-off flows; configure DFx mode, triage violations, develop waivers, and drive fixes with design teams.
Define and maintain RTL-to-SDC timing-constraint methodology across diverse intellectual property blocks.
Manage Spyglass reset domain crossing sign-off flows, perform reset-domain analysis, triage violations, develop waivers, and introduce robust reset scenarios with verification teams.
Lead Conformal LEC formal equivalence checking (RTL-to-RTL and RTL-to-gate), debug failures, create constraints, and conduct sign-off reviews.
Automate and enhance methodology flows using TCL and Python scripting.
Collaborate with RTL design, design for test, timing, and physical design groups to scale methodologies across the full system-on-chip.

Category	Tesla SI
Location	Austin, Texas
Requisition ID	266525
Type	Full-time

Job Description

<p>The Tesla SI Hardware team is at the forefront of revolutionizing artificial intelligence through cutting-edge hardware innovation. Comprising brilliant engineers and visionaries, the team designs and develops advanced SI inference chips tailored to accelerate Tesla’s machine learning capabilities. A key part of this effort is Dojo, Tesla's custom supercomputer system built to efficiently train massive neural networks on vast video data from the fleet. The work of Tesla's SI Hardware team powers the neural networks behind Full Self-Driving (FSD), and Tesla humanoid robot, Optimus, pushing the boundaries of computational efficiency and performance. By creating custom silicon and optimized architectures, the team ensures Tesla remains a leader in SI-driven automotive and energy solutions, shaping a future where intelligent machines enhance human life.</p><p>This role focuses on developing and owning the EDA methodology flows that enable SOC design signoff, spanning RTL integration, static verification, formal equivalence checking, and timing constraint development across a large multi-block SOC. </p>

Job Responsibilities

Own RTL‑to‑PD integration and Spyglass lint sign‑off flow, including filelist methodology, violation triage, and waiver creation
Set up, run, and maintain Spyglass CDC sign‑off flows, configure DFx mode, triage violations, develop waivers, and drive fixes with design teams
Define and maintain RTL‑to‑SDC timing‑constraint methodology across diverse IP blocks
Manage Spyglass RDC sign‑off flows, perform reset‑domain analysis, triage violations, develop waivers, and introduce robust reset scenarios with verification teams
Lead Conformal LEC formal equivalence checking (RTL‑to‑RTL, RTL‑to‑gate), debug failures, create constraints, and conduct sign‑off reviews
Automate and enhance methodology flows using TCL and Python scripting
Collaborate with RTL design, DFT, timing, and physical design groups to scale methodologies across the full SOC

Job Requirements

Degree in Electrical Engineering, Computer Engineering, or equivalent experience
2+ years of industry experience (including internships) working with digital design EDA tools
Hands-on experience with one or more: Spyglass (CDC/lint/RDC), Conformal LEC, Formality, or equivalent
Understanding of clock domain crossings, reset synchronization, and synthesis fundamentals
Proficiency in TCL and/or Python scripting
Familiarity with SDC constraint development
Elementary understanding of DFx/DFT scan modes and their impact on CDC and constraints
Experience with both Synopsys and Cadence EDA tool ecosystems
Exposure to RTL filelist management and build systems at SOC scale
Experience with physical design flows (synthesis, PnR, timing analysis)

About the Company

Tesla

Makes electric cars, robotaxis and grid batteries

Tesla makes electric cars and batteries that store power for homes and utilities, and it develops self-driving software and humanoid robots. In 2023, its Model Y became the first electric vehicle to rank as the world's best-selling car. Buyers order the Model 3 sedan, Model Y SUV, or Cybertruck pickup directly from Tesla instead of through dealers, and they charge on its Supercharger fast-charging network. It also sells Megapack and Powerwall batteries, runs a robotaxi service, and charges drivers a monthly fee for self-driving software that still needs their supervision. Tesla was founded in 2003, with Elon Musk as its lead early investor and a recognized co-founder, and it is based in Austin, Texas.

Company size: 10,001+
Company stage: IPO
Headquarters: Austin, TX
Founded: 2003

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