E

Eliyan

D2D/C2C interconnect IP licensing

Principal Physical Design Engineer

Full-Time
No salary listed
Senior, Expert
San Francisco Bay Area, CA, USA
In Person
Hardware Engineering

About the job

Requirements
  • 8 to 12 years of ASIC physical design experience, owning floorplanning, integration, clocking, and power planning from early feasibility through signoff and tapeout on complex systems-on-chip.
  • Expertise in architecture- and package-driven hierarchy planning, Lego-aligned boundaries, pin strategy, feedthrough and repeater planning, bus planning, and clock-tree-synthesis methodologies including spine and rib, H-tree, or mesh.
  • Awareness of electromigration, IR drop, physical verification, and static timing analysis, with experience in multi-mode multi-corner analysis and library-corner skew-group balancing.
  • Exposure to advanced process nodes such as TSMC 3 nm, TSMC 2 nm, or Samsung 2 nm.
  • Experience with functional engineering change order execution.
Responsibilities
  • Drive the development of application-specific integrated circuits from register-transfer level to graphic database system II.
  • Oversee and optimize the complete design flow, including synthesis, place-and-route, static timing analysis, electromigration and IR drop analysis, and physical verification.
  • Develop and improve design flows and methodologies to ensure high-quality, on-time delivery.
  • Perform architecture- and packaging-driven floorplanning and integration so physical partitions match system and package constraints.
  • Define boundaries with pin alignment and consistent interface placement across chips and blocks.
  • Plan feedthroughs, repeaters, and buses, reserving routing corridors, layers, and resources for cross-block connectivity.
  • Define clocking architecture methodology, selecting spine and rib, H-tree, or mesh to optimize power, skew, latency, and robustness.
  • Establish clock-tree-synthesis methodology, including skew and latency targets, buffer and integrated clock-gating strategy, non-default routing and shielding rules for critical clock routes.
  • Define skew groups and balancing strategy across library corners, ensuring consistent behavior under multi-mode multi-corner variations and derates.
  • Drive clock-constraint quality across the hierarchy with clean chip-to-block and block-to-chip handoffs for signoff readiness.
  • Define design-rule-check-aware power-grid architecture, including rings, straps, and mesh, matching metal-resistivity assumptions to IR-drop targets and electromigration limits.
  • Plan analog routing with keepouts, shielding, spacing, and grid-topology choices that preserve sensitive nets and meet design-rule checks.
  • Drive aligned power-mesh alignment across top-level, subsystem, and block levels with consistent strap pitch, via patterns, and clean connectivity.
  • Lead early and signoff electromigration and IR-drop analysis, identify hotspots, and implement grid reinforcement and via optimization without routing or congestion penalties.
  • Align power planning with floorplan and package constraints, including bump map, current demand, and entry points, to minimize noise and IR drop.

About the company

E

Eliyan

View
Website

Eliyan provides high-performance interconnect IP and chiplet products for chiplet-based systems. Its NuLink PHY enables die-to-die and chip-to-chip connections with simultaneous bidirectional signaling, delivering high bandwidth on standard organic substrates and reducing dependency on expensive advanced packaging. The company licenses IP cores and offers NuGear memory/I-O chiplets and a Universal Memory Interface to connect ASICs with multiple memory types, compatible with UCIe and BoW standards. Eliyan aims to help data centers, AI accelerators, and HPC developers build scalable, cost-effective multi-die systems with improved system performance.

Company Size

51-200

Company Stage

Series C

Total Funding

$295M

Headquarters

Santa Clara, California

Founded

2021

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Simplify Jobs

Simplify's Take

What believers are saying

  • Eliyan closed a $145 million Series C on July 29, 2026.
  • Cisco Investments and Lumentum joined in July 2026, validating optical and infrastructure demand.
  • Initial chiplet shipments are expected in 2026, with low-millions revenue rising toward 2027.

What critics are saying

  • PhotonIC sued Eliyan in June 2026 over breach, fraud, and trade secrets claims.
  • NuLink-XD launched July 24, 2026 without named customers, volumes, or revenue commitments.
  • Broadcom, Marvell, and Nvidia still own critical AI connectivity, threatening Eliyan's standalone relevance.

What makes Eliyan unique

  • Ramin Farjadrad's SBD signaling doubles bandwidth on standard organic substrates, not just advanced packaging.
  • Eliyan's NuLink-XD and NuGear span die-to-die, chip-to-module, and memory interfaces.
  • Arm Total Design and OCP participation make Eliyan an open chiplet infrastructure player.

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Benefits

  • Health Insurance
  • Paid Vacation
  • Flexible Work Hours

Growth & Insights and Company News

Headcount

6 month growth

3%

1 year growth

1%

2 year growth

2%
Gold Flag Media LLC
Oct 14th, 2026
Eliyan introduces NuLight optical interconnect chiplets.

Eliyan introduces NuLight optical interconnect chiplets. Eliyan today introduced the Nexus(TM) and Oscar(TM) NuLight(TM) chiplets, the world's first 2D microVCSEL interconnect platform designed to extend AI scale-up connectivity beyond the practical bandwidth and reach limits of copper. The platform includes Nexus, a 1.6T reverse gearbox, and Oscar, an electrical interface chip (EIC) that connects high-speed electrical interfaces to microVCSEL and photodiode optical arrays. Together, they provide scalable building blocks for linking compute resources across large AI systems, providing the enhanced reach, low power, and high reliability that these systems demand. Eliyan CEO and co-founder Ramin unveiled the technology at this week's OCP Summit 2026 with a presentation detailing the technology architecture and products. Addressing the Copper Wall As AI scale-up domains expand across multiple racks, copper connections face increasing constraints in delivering both high bandwidth and longer reach. Eliyan's NuLight platform addresses this "copper wall" with a high-bandwidth, high-density architecture that spreads bandwidth across more optical lanes operating at lower data rates than standard PAM4 SerDes connections. Parallel non-return-to-zero (NRZ) optical signaling simplifies per-lane signal processing, enabling more power-efficient optical links than traditional optical interconnects. The microVCSEL-based architecture targets an initial optical reach of approximately 50 meters, with a design objective of combining optical reach with copper-like reliability, availability, and operating characteristics. "Scaling AI infrastructure requires efficient, reliable connectivity that reaches beyond a single rack," said Ramin Farjadrad, co-founder and CEO of Eliyan. "We have pioneered another breakthrough interconnect technology that we created from the ground up to solve the copper wall in the AI data center. The industry's rapid adoption of our proposed 2D microVCSEL interconnect proves Eliyan is on the right track again. With our NuLight chiplet platform, customers can scale aggregate bandwidth through reusable building blocks. At the same time, on-the-fly lane repair addresses the reliability requirements of large AI scale-up and scale-in networks. This is the next step in expanding our platform across the AI connectivity path." Nexus Bridges High Speed Electrical Interfaces and Parallel Optics Designed in TSMC 3nm, Nexus combines power-efficient, configurable-reach 212G PAM4 SerDes with reverse gearbox functionality and high-speed die-to-die connectivity. Its compact footprint supports tight coupling with optical components. The reverse gearbox distributes each high-speed PAM4 electrical channel across four lower-speed NRZ channels, providing the electrical bridge to slow-and-wide optical arrays while supporting fully retimed implementations. Nexus includes advanced telemetry with forward error correction (FEC) monitoring, termination and regeneration, as well as support for IEEE auto-negotiation and host link training. These capabilities support link diagnostics and management in dense optical systems. Oscar Interfaces with microVCSEL and Photodiode Arrays Oscar complements Nexus with laser-driver and TIA electrical interfaces to vertical-cavity surface-emitting lasers (VCSELs) and photodiode arrays in very dense arrays, with state-of-the-art crosstalk cancellation and heat-management schemes. Optical Lane Repair Supports Reliable AI Connectivity The platform uses patented technology for its on-the-fly repair architecture that uses spare optical lanes to protect active links. If a lane degrades or fails, the architecture redirects traffic to a spare lane without interrupting link operation. Combined with link diagnostics, this capability meets a critical requirement for AI scale-up and scale-in networks, where interconnect failures cause costly downtime and interrupt massive AI processing operations. A Modular Platform from OSFP to Co-Packaged Optics (CPO) The NuLight platform provides a path to co-packaged optics (CPO), where future versions of Oscar will interface directly with host ASICs using die-to-die connectivity. NuLight's microVCSEL array approach draws on mature, highly available GaAs laser technology and avoids the need for external indium-phosphide lasers in the optical engine. Shannon, writes, edits and produces Semiconductor Digest's news articles, email newsletters, blogs, webcasts, and social media posts. She holds a bachelor's degree in journalism from Huntington University in Huntington, IN. In addition to her years of freelance business reporting, Shannon has also worked in marketing and public relations in the renewable energy and healthcare industries.

Yahoo Finance
Oct 14th, 2026
Eliyan unveils NuLight microVCSEL chiplets to break AI's copper wall, scaling to 12.8Tbps

Eliyan has introduced NuLight, which it calls the first 2D microVCSEL interconnect platform for AI scale-up networks. The Santa Clara company says it aims to get past the "copper wall," the bandwidth and reach limits of copper links in large AI systems. The platform pairs two chiplets. Nexus is a 1.6Tbps reverse gearbox, and Oscar is an interface chip for microVCSEL and photodiode arrays. Both are sampling now. The design targets an initial optical reach of about 50 metres. Modular 1.6Tbps slices scale to 6.4Tbps and 12.8Tbps configurations, with a path toward co-packaged optics. A spare-lane repair feature reroutes traffic if a lane fails, without interrupting the link. Chief executive Ramin Farjadrad unveiled the technology at OCP Summit 2026.

HPCwire
Oct 14th, 2026
Eliyan targets copper interconnect limits with NuLight chiplet platform.

Eliyan targets copper interconnect limits with NuLight chiplet platform. October 14, 2026 Press play to listen to this content SANTA CLARA, Calif., Oct. 14, 2026 - Eliyan, a leader in foundational connectivity products enabling next-generation AI compute, memory, and networking systems, today introduced the Nexus and Oscar NuLight chiplets, the world's first 2D microVCSEL interconnect platform designed to extend AI scale-up connectivity beyond the practical bandwidth and reach limits of copper. The platform includes Nexus, a 1.6T reverse gearbox, and Oscar, an electrical interface chip (EIC) that connects high-speed electrical interfaces to microVCSEL and photodiode optical arrays. Together, they provide scalable building blocks for linking compute resources across large AI systems, providing the enhanced reach, low power, and high reliability that these systems demand. Eliyan CEO and co-founder Ramin unveiled the technology at this week's OCP Summit 2026 with a presentation detailing the technology architecture and products. Addressing the Copper Wall As AI scale-up domains expand across multiple racks, copper connections face increasing constraints in delivering both high bandwidth and longer reach. Eliyan's NuLight platform addresses this "copper wall" with a high-bandwidth, high-density architecture that spreads bandwidth across more optical lanes operating at lower data rates than standard PAM4 SerDes connections. Parallel non-return-to-zero (NRZ) optical signaling simplifies per-lane signal processing, enabling more power-efficient optical links than traditional optical interconnects. The microVCSEL-based architecture targets an initial optical reach of approximately 50 meters, with a design objective of combining optical reach with copper-like reliability, availability, and operating characteristics. "Scaling AI infrastructure requires efficient, reliable connectivity that reaches beyond a single rack," said Ramin Farjadrad, co-founder and CEO of Eliyan. "We have pioneered another breakthrough interconnect technology that we created from the ground up to solve the copper wall in the AI data center. The industry's rapid adoption of our proposed 2D microVCSEL interconnect proves Eliyan is on the right track again. With our NuLight chiplet platform, customers can scale aggregate bandwidth through reusable building blocks. At the same time, on-the-fly lane repair addresses the reliability requirements of large AI scale-up and scale-in networks. This is the next step in expanding our platform across the AI connectivity path." Nexus Bridges High Speed Electrical Interfaces and Parallel Optics Designed in TSMC 3nm, Nexus combines power-efficient, configurable-reach 212G PAM4 SerDes with reverse gearbox functionality and high-speed die-to-die connectivity. Its compact footprint supports tight coupling with optical components. The reverse gearbox distributes each high-speed PAM4 electrical channel across four lower-speed NRZ channels, providing the electrical bridge to slow-and-wide optical arrays while supporting fully retimed implementations. Nexus includes advanced telemetry with forward error correction (FEC) monitoring, termination and regeneration, as well as support for IEEE auto-negotiation and host link training. These capabilities support link diagnostics and management in dense optical systems. Oscar Interfaces with microVCSEL and Photodiode Arrays Oscar complements Nexus with laser-driver and TIA electrical interfaces to vertical-cavity surface-emitting lasers (VCSELs) and photodiode arrays in very dense arrays, with state-of-the-art crosstalk cancellation and heat-management schemes. Optical Lane Repair Supports Reliable AI Connectivity The platform uses patented technology for its on-the-fly repair architecture that uses spare optical lanes to protect active links. If a lane degrades or fails, the architecture redirects traffic to a spare lane without interrupting link operation. Combined with link diagnostics, this capability meets a critical requirement for AI scale-up and scale-in networks, where interconnect failures cause costly downtime and interrupt massive AI processing operations. A Modular Platform from OSFP to Co-Packaged Optics The NuLight platform provides a path to co-packaged optics (CPO), where future versions of Oscar will interface directly with host ASICs using die-to-die connectivity. NuLight's microVCSEL array approach draws on mature, highly available GaAs laser technology and avoids the need for external indium-phosphide lasers in the optical engine. Availability Both Nexus and Oscar chiplets are sampling now. About Eliyan Eliyan Corporation develops advanced connectivity technologies that enable next-generation AI, cloud, and high-performance computing systems. Its portfolio of differentiated interconnect technologies, memory expansion, and chiplet solutions addresses critical bandwidth, power efficiency, and scalability challenges across modern compute infrastructure. Eliyan's technologies enable customers to build higher-performance systems with greater memory capacity, improved power and area efficiency, and most importantly, higher bandwidth at lower cost. For more information, visit www.eliyan.com. Silicon to systems engineering is reshaping HPC for manufacturing As product design becomes more interconnected,... For all the talk about a shortage of AI computing power, and the need for... Most engineers know what an overloaded web service looks like. Latency goes up. Queues start... A new study from Google and MIT finds that AI is accelerating the scientific process,... Apparently, America's new AI data centers are going to drink us dry. If you've followed... Neoclouds are spending a fortune on GPUs, and they need to keep those GPUs doing...

InfraSale
Oct 9th, 2026
Eliyan receives takeover bid following $1 billion Series C funding.

Eliyan receives takeover bid following $1 billion Series C funding. October 9, 2026 Eliyan has attracted a takeover bid after securing $1 billion in Series C funding. This development highlights the growing interest in battery energy storage systems (BESS) as demand surges for long-duration energy solutions. InfraSale's audience should monitor how this bid may impact the competitive landscape in the BESS market. investment battery storage renewables

Data Center Dynamics
Jul 31st, 2026
Chiplet interconnect startup Eliyan valued at $1bn following $145m Series C funding round.

Chiplet interconnect startup Eliyan valued at $1bn following $145m Series C funding round. Umesh Padval, managing partner of Seligman Ventures, will also join the company's board July 31, 2026 Chiplet interconnect manufacturer Eliyan has raised $145 million in a Series C funding round, valuing the startup at $1 billion. The oversubscribed round was led by Seligman Ventures, with participation from both new and existing investors, including Cisco Investments and Lumentum. In addition to the funding, Umesh Padval, managing partner of Seligman Ventures, will join Eliyan's Board of Directors. In a statement, Eliyan said the financing will support the development of its next-generation interconnect technologies and allow the company to expand its ecosystem partnerships and scale manufacturing. Founded in 2021 by Ramin Farjadrad, the former CTO and VP of networking at Marvell Semiconductor, along with Syrus Ziai, and Patrick Soheili, Eliyan's chiplet interconnect technology speeds up the processing for AI chips, with the company claiming it achieves up to four times the performance and half the power of other solutions. The company's NuLink PHY and NuGear offerings address both die-to-die and die-to-memory interconnect challenges through its Universal Memory Interface (UMI), a bi-directional interconnect method that enables a bandwidth-efficient connection to memory, in both standard organic substrates and advanced packaging. Chiplets are tiny integrated circuits with specialized functions, which can be combined to make larger integrated circuits. They contain multiple smaller dies, instead of one monolithic die. "AI infrastructure is undergoing one of the largest architectural transitions in computing history," said Farjadrad, who is Eliyan's CEO. "As compute, memory, packaging, and networking become increasingly interconnected, traditional approaches to system connectivity are reaching their limits. Eliyan was founded to address these challenges at the architectural level. This financing, together with the support of leading strategic and financial investors, positions us to accelerate product development, customer adoption, and ecosystem expansion as we help enable the next generation of AI infrastructure." More in investment / M&A / financing.