Cadence Design Systems

Develops EDA software, IP, verification tools

Principal Product Engineer

Silicon & ASIC DesignConfirmed live in the last 24 hours

Full-timeBengaluru, Karnataka, IndiaNo salary listedIn-person

About the Job

Requirements

A Bachelor’s degree with at least 12–15 years of design or electronic design automation experience, or a Master’s degree with at least 10 years of experience, is required.
Strong knowledge of digital design flows, static timing analysis, and electromigration and IR drop is required.
Prior experience with application-specific integrated circuit digital implementation flows and electronic design automation tools is required.
Experience with advanced FinFET nodes at 7nm and below is required.
Good programming knowledge in Unix, shell scripting, Perl, and Tcl is required.
Strong customer-facing communication and problem-solving skills are required.
Strong personal drive for continuous learning and expanding professional skill sets is required.
Excellent verbal and written communication skills are required.
Familiarity with electronic design automation tool operation, setup, and debugging is required, including Genus, Innovus, Tempus, and Voltus.

Responsibilities

Interface with customers regarding digital reference flow requirements, including synthesis, floorplanning, clock tree synthesis, power planning, place and route, timing closure, and sign-off.
Capture reference flow requirements and scope effort for reference flow development.
Create baseline flows for customers to use as starting points for digital implementation.
Use baseline flows to implement test cases for process certification and validation.
Use implementation test cases for Tempus and Voltus sign-off.
Create documentation explaining the theory and use behind reference flow steps and commands.
Perform power, performance, and area optimization.

Desired Qualifications

A Master’s degree is preferred.
Experience with gate-all-around technologies at 2nm and below is preferred.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

This position involves:

Interfacing with customers regarding digital reference flow requirements, including
- Synthesis
- Floorplanning
- Clock tree synthesis
- Power planning
- Place and route
- Timing closure
- Sign-off
Capturing reference flow requirements, scoping effort on reference flow development
Creating baseline flows to be used by customers as starting point for digital implementation
Using baseline flow to implement test cases for process certification and validation
Using implementation testcases for Tempus and Voltus sign-off
Creating documentation explaining the theory and use behind reference flow steps and commands
PPA optimization

Position requires:

Bachelor’s degree with at least 12-15 years of design/EDA experience or Master’s degree with at least 10 years of experience. Master’s degree preferred.
Strong knowledge in Digital Design Flows, Static Timing Analysis and EMIR is required
Prior experience with ASIC digital implementation flows and EDA tools is required; Experience with advanced FinFet nodes (7nm and below) required. Experience with GAA technologies (2nm and below) preferred.
Good programming knowledge in Unix, Shell scripting, perl and importantly TCL
Strong customer-facing communication and problem-solving skills
Strong personal drive for continuous learning and expanding professional skill sets
Excellent verbal and written communication skills

Familiar with EDA tool operation, setup and debug:

Digital: Genus, Innovus, Tempus, Voltus, etc

We’re doing work that matters. Help us solve what others can’t.

About the Company

Cadence Design Systems

Develops EDA software, IP, verification tools

Cadence Design Systems supplies software, hardware, and IP for electronic design automation (EDA) to help customers create advanced semiconductor chips and electronic systems. Its tools handle system design, verification, digital and analog IC design, and custom flows, while IP such as Tensilica processors and DSP cores can be licensed for integration into customer products. The offerings are delivered as software licenses with maintenance and support, plus IP licensing and occasional hardware-accelerated options. The company differentiates itself with a broad, end-to-end EDA portfolio and close collaboration with industry leaders to streamline the path from concept to silicon, aiming to help customers bring sophisticated silicon and electronics to market faster with lower risk and higher productivity.

Company size: 10,001+
Company stage: IPO
Headquarters: San Jose, CA
Founded: 1988

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