Qualcomm

Designs mobile chips and licenses wireless patents

Staff Physical Design Engineer

Silicon & ASIC DesignConfirmed live in the last 24 hours

Full-timeHod Hasharon, IsraelNo salary listedIn-person

About the Job

Requirements

At least 3 years of experience in digital physical design (backend) methodologies, with the posting's minimum qualifications also specifying 4+ years with a bachelor's degree, 3+ years with a master's degree, or 2+ years with a PhD in ASIC design, verification, validation, integration, or related work experience.
Experience with advanced process nodes such as TSMC N5, N4P, N3, or equivalent FinFET processes.
Proficiency in Synopsys ICC2, Cadence Innovus, Calibre, PrimeTime, RedHawk, or Voltus electronic design automation tools.
Strong understanding of floorplanning, clock tree synthesis, place and route, static timing analysis, IR drop and electromigration analysis, and power optimization.
Scripting skills in Python and TCL, including the ability to build and maintain design automation flows.
Hands-on flow development experience, including building reusable scripts, run environments, and regression frameworks.
Bachelor's degree in Science, Engineering, or a related field and 4+ years of applicable experience, or a Master's degree in those fields and 3+ years, or a PhD in those fields and 2+ years.

Responsibilities

Own block-level and subsystem-level physical implementation, driving timing closure and physical sign-off on advanced process nodes.
Lead floorplanning, placement, clock tree synthesis, routing, and optimization for high-speed digital blocks and subsystems.
Drive timing closure, including clock skew balancing, on-chip variation handling, multi-corner multi-mode analysis, and engineering change order implementation.
Conduct and own signal integrity, power integrity, IR drop, and electromigration analysis using tools such as RedHawk or Voltus.
Run full signoff verification flows, including design rule checking, layout versus schematic, design for manufacturability, and electromigration/IR analysis.
Develop and maintain backend physical design flows using Python and TCL-based automation for place and route, static timing analysis, and physical verification.
Integrate Agentic AI methodologies and AI-assisted tools for constraint optimization, timing engineering change order suggestions, and violation triage.
Optimize power and area through multi-threshold voltage optimization, clock gating, and power-aware synthesis.
Collaborate with front-end, design-for-test, verification, and process teams to resolve design and manufacturing issues.

Desired Qualifications

Familiarity with design-for-test concepts such as scan insertion, automatic test pattern generation, and built-in self-test.
Exposure to or curiosity about Agentic AI-driven electronic design automation methodologies.

Company:

Qualcomm Israel Ltd.

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.

About the Role

As a Senior Physical Design Engineer, you will take ownership of block-level and subsystem-level physical implementation, driving timing closure and physical sign-off on advanced process nodes. You will also contribute to flow development and begin integrating Agentic AI methodologies into the team's design automation practices.TSMC N5 / N4P / N3Python • TCLAgentic AIFlow DevelopmentMulti-Patterning

What You'll Do

Lead floorplanning, placement, CTS, routing, and optimization for high-speed digital blocks and subsystemsDrive timing closure including clock skew balancing, OCV handling, MCMM analysis, and ECO implementationConduct and own signal integrity, power integrity, IR drop, and electromigration analysis (RedHawk / Voltus)Run full signoff verification flows (DRC, LVS, DFM, EM/IR,)Develop and maintain backend PD flows using Python and TCL-based automation for PnR, STA, and physical verificationDrive Agentic AI integration — leverage AI-assisted tools for automated constraint optimization, timing ECO suggestions, and intelligent violation triageOptimize power and area via Multi-Vt optimization, clock gating, and power-aware synthesisCollaborate cross-functionally with front-end, DFT, verification, and process teams to resolve design and manufacturing issues

What You'll Need

3–8 years of experience in digital Physical Design (Backend) methodologies
Experience with advanced process nodes (TSMC N5, N4P, N3, or equivalent FinFET)Proficiency in EDA tools: Synopsys ICC2, Cadence Innovus, Calibre, PrimeTime, RedHawk / VoltusStrong understanding of floorplanning, CTS, PnR, STA, IR drop/EM analysis, and power optimizationSolid scripting skills in Python and TCL — ability to build and maintain design automation flowsHands-on flow development experience: building reusable scripts, run environments, and regression frameworksExposure to or curiosity about Agentic AI-driven EDA methodologiesFamiliarity with DFT concepts (scan insertion, ATPG, BIST) is a plus

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

*References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [email protected] or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

To all Staffing and Recruiting Agencies:Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.

If you would like more information about this role, please contact Qualcomm Careers.

About the Company

Qualcomm

Designs mobile chips and licenses wireless patents

Qualcomm designs the Snapdragon processors and modems inside many Android phones, and it licenses its wireless patents to device makers around the world. It helped commercialize CDMA, the cellular technology behind 3G networks, and its patents cover core parts of the 4G and 5G standards that phones use to connect. The company does not run its own chip factories; contract foundries make its chips, which it sells to makers of phones, PCs, cars, and connected devices. Device makers also pay Qualcomm royalties for using its patented technology, which forms a second business alongside chip sales. Qualcomm was founded in 1985 and is based in San Diego, California.

Company size: 10,001+
Company stage: IPO
Headquarters: San Diego, CA
Founded: 1985

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