Layout/Mask Design

Summary

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Minimum Qualifications

Bachelor's degree or foreign equivalent in Electrical Engineering or related field and 2 years of experience in the job offered or related occupation. Experience and/or education must include: Using layout floor-planning, standard cell planning and hierarchical layout assembly to generate best PPA (power, performance and area) layouts. Resolving issues with RC delay, electromigration, self-heating and cross capacitance. Recognizing failure prone layout structures, working with designers for the best approach to problems including shielding critical signals, analyzing DFM yields, and LOD effects. Creating layouts with a robust PG grid using IR simulations tools. Collaborating and communicating effectively with multi-functional teams to understand engineering spec and have on-time deliverables. Interpreting CALIBRE DRC, ERC, LVS, and DFM reports to finish layout(s). Using CADENCE virtuoso layout design tools to draw layouts and increase productivity.

Preferred Qualifications

N/A

Description

APPLE INC has the following available in Austin, Texas. Design complex custom layout for digital circuits in deep SubMicron CMOS technologies. Work with Layout lead and circuit designers to review and analyze floorplans of complex circuits. Responsible to run a complete set of layout design verification tools available and clean up megacells to match engineering specifications. Work with Layout lead and circuit design team to plan, schedule work and negotiate layout tradeoffs as needed. Interpret LVS, DRC and ERC report to find the fastest way to complete layouts. Utilize advanced CAD tools, mask design knowledge to layout corrections and robust physical design representation of circuits. Utilize advanced layout techniques to come up with best-in-class PPA for critical designs. Work with design lead to review EMIR simulations and apply necessary fixes to achieve robust power delivery. Utilize automated P&R tools to speed up the layout execution of digital designs. 40 hours/week.