Senior or Staff Hardware Design Engineer
About the job
- A Master of Science or Ph.D. in electrical engineering or a related field is required.
- At least 5 years of hands-on hardware system design experience is required.
- Proven experience as a technical lead or system lead is required.
- Experience working with supply chain vendors is required.
- Demonstrated leadership and mentorship capabilities are required.
- Define and drive overall hardware system architecture and top-level specifications.
- Lead hardware system design and system integration.
- Perform high-level feasibility analysis and risk assessment.
- Review and approve hardware designs to ensure architectural alignment.
- Drive system bring-up strategy and debug execution.
- Perform hardware system design.
- Conduct schematic design, simulation, analysis, and optimization to meet performance targets.
- Provide PCB layout guidance and collaborate closely with PCB layout engineers to ensure design intent is met.
- Collaborate with PI/SI engineers to ensure proper PDN performance.
- Participate in design reviews and contribute to design documentation.
- Participate in silicon bring-up, characterization, and debugging.
- Follow best practices for hardware system design, verification, and signoff.
- Experience in server motherboard design.
- Familiarity with power delivery design and component choice for high-performance server systems.
- Good communication skills and ability to work in a collaborative team environment.
About the company
PowerLattice designs power delivery chiplets that attach to the processor package and regulate voltage directly at the compute die. The monolithic chiplet combines on-die magnetic inductors, voltage control circuits, vertical packaging, and a programmable software layer on a single silicon die, bringing power delivery closer to the cores. This approach reduces total compute power by over 50% and can double performance while easing cooling, and it is scalable for AI accelerators, GPUs, and data-center processors. The company sells these chiplets to hyperscalers, OEMs, and system integrators, with early trials planned for 2026, aiming to improve energy efficiency and compute performance through near-die, integrated power regulation.
Company Size
11-50
Company Stage
Series A
Total Funding
$25M
Headquarters
Vancouver, Washington
Founded
2023
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Simplify's Take
What believers are saying
- The company raised $25 million in November 2025, totaling $31 million for expansion.
- Management claims the chiplet cuts compute power needs by over 50%, a powerful buyer pitch.
- 2026 hiring in analog, packaging, and SoC roles signals active productization and customer readiness.
What critics are saying
- PowerLattice still relies on unnamed pilot customers, with broader trials only slated for first-half 2026.
- ADI bought Empower Semiconductor in 2026, intensifying competition from better-funded vertical power rivals.
- If yields, thermal limits, or customer adoption stall, PowerLattice becomes a stranded chiplet vendor.
What makes Powerlattice unique
- Pat Gelsinger joined the board after PowerLattice's November 2025 stealth exit.
- PowerLattice integrates voltage regulation into the processor package, reducing power loss dramatically.
- TSMC is producing first chiplets, proving the design moved beyond concept.
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Benefits
Health Insurance
Dental Insurance
Vision Insurance
Stock Options
Hybrid Work Options
Growth & Insights and Company News
6 month growth
0%1 year growth
-11%2 year growth
-11%PowerLattice raised $25M led by Playground Global and Celesta. The company’s chiplet cuts compute power needs by >50%, breaking the "AI power wall."