System Modelling Engineer
Vertical Compute
System Modelling Engineer
Vertical Compute
Chiplet-based memory-compute integration for edge AI
About Us : AI compute is hitting a hard physical wall, and memory bottlenecks are throttling the entire industry. Founded in October 2024 and backed by €57M in funding, Vertical Compute is solving this with proprietary Vertical Integrated Memory (VIM™) chiplets, making AI hardware faster, greener, and vastly more scalable. We are an interdisciplinary team transforming breakthrough semiconductor physics into commercial reality.
Why Now : After 18 months of intensive R&D, Vertical Compute has reached a critical inflection point. Our underlying technology is validated, and we have successfully met our core technical milestones. Armed with a proven technical data package and ongoing system studies, we are now shifting from pure R&D to active engagement with global enterprise customers. As we prepare for our next phase of scale and growth starting in 2027, joining us today means taking direct ownership of the hardware foundation that will power the next era of AI compute.
About the role:
We are looking for an expert System Modelling Engineer to drive the modelling, integration, and performance analysis of our advanced Vertical Compute / VIMx system memory architectures.
In this role, you will be responsible for building robust SystemC models, integrating them onto the Palladium emulation platform, and benchmarking performance against an ideal SRAM baseline for cutting-edge AI applications.
Key Responsibilities:
System-Level Modeling: Design, validate, and deliver robust SystemC software models for individual VIMx components and the broader memory hierarchy.
Multi-Bank Configurations: Model and simulate complex multi-bank system memory configurations to evaluate latency, throughput, and system behavior.
Emulation Platform Integration: Deploy and configure completed SystemC memory models onto the Cadence Palladium emulation platform.
Co-Simulation & Validation: Ensure seamless interface and operational stability between the emulation environment and the memory models.
Performance Evaluation & AI Benchmarking: Execute AI application benchmarks on the Palladium platform.
Value Demonstration: Deliver a detailed performance evaluation report contrasting the VIM system memory architecture against an ideal SRAM baseline across key metrics (latency, bandwidth, energy efficiency, and area) to prove the benefits of VIM.
About the team:
This role is part of the Product & system team, partnering closely with our cross-functional engineering teams in Product & system and Memory Design. We foster a highly collaborative, inclusive environment where strong alignment, high transparency and seamless team coordination are central to our shared success.
Chiplet-based memory-compute integration for edge AI
Vertical Compute develops chiplet-based technology that vertically integrates memory and compute to address the AI memory wall. It stacks high-aspect-ratio vertical data lanes above compute units, so data moves over nanometres instead of across long traces, improving energy use, density, and performance for AI at the edge. The company differentiates itself by co-designing memory and compute in a vertical chiplet stack to achieve higher density and lower data-transfer energy than traditional DRAM approaches, with a focus on privacy-preserving edge AI. Its goal is to move from seed funding to commercialization by building its engineering team and bringing its vertical memory-compute technology to market.
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