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MaxLinear

Fabless RF/analog/mixed-signal IC designer

Senior Principal Digital SoC Design Engineer

Silicon & ASIC DesignUpdated on Nov 10
Full-timeSan Jose, CA, USAIn-person

About the Job

Requirements

  • Deep hands-on expertise in SystemVerilog/Verilog RTL design, SoC micro-architecture, and complex top-level integration.
  • Strong working knowledge of USB 2.0/3.x device and host architectures, including xHCI, and PCIe endpoint architecture, with experience integrating licensed controller and PHY IP.
  • Experience with serial and peripheral interfaces, including UART, I²C/I3C, SPI, and GPIO, and bridge-type data paths, FIFOs, and DMA.
  • Experience integrating embedded Arm processor subsystems, DDR/memory controllers, bus fabrics such as AMBA AXI/AHB/APB, and security IP.
  • Strong understanding of clock/reset, CDC/RDC, low-power design, timing constraints, synthesis, DFT, and physical design trade-offs.
  • Track record delivering multiple SoCs from architecture through tapeout, silicon bring up, compliance certification, and high-volume production.
  • Experience working with external design partners and IP vendors, and ability to lead technically across multiple disciplines and global teams.
  • BS in Electrical Engineering or related with 15 years of experience, or MS with 12 years of experience, or Ph.D. with 9 years of experience.

Responsibilities

  • Lead digital architecture and RTL for USB device-side connectivity bridges, including multi-port serial (UART), I²C/SPI/GPIO bridging, endpoint/FIFO architecture, flow control, and OTP-based configurability and customization.
  • Architect and integrate PCIe-to-USB host bridge solutions, including PCIe endpoint and USB host controller (xHCI) integration, DMA engines, buffer management, interrupt and power-state handling, and driver-visible register architecture.
  • Define and lead digital architecture for complex embedded-processor SoCs for data center platform management, including multi-core Arm subsystems, memory controllers, high-speed host interfaces, sideband management buses, and peripheral-rich I/O.
  • Drive platform security and management features, including secure boot, hardware root of trust, cryptographic checksum generator and checker, and host-to-management communication paths.
  • Maximize reuse of existing digital IP across product generations, and drive make, reuse, or license decisions for USB, PCIe, and other interface controllers and PHYs.
  • Define on-chip interconnect, clock/reset, low-power, and DFT architecture, and own RTL quality through lint, CDC/RDC, synthesis, timing constraints, and implementation closure.
  • Set verification strategy with the DV team, including compliance and interoperability readiness, emulation/FPGA prototyping, and firmware/driver co-verification.
  • Partner closely with analog/mixed-signal, PHY, firmware, software, package, test, and applications teams from concept through silicon bring up, compliance, qualification, and production.
  • Mentor senior engineers, lead design reviews, and act as the digital technical authority across the connectivity and SoC roadmap.

Desired Qualifications

  • Familiarity with data center server management concepts such as eSPI, I3C, MCTP, and hardware root of trust.

About the Company

MaxLinear

Fabless RF/analog/mixed-signal IC designer

MaxLinear designs and sells RF, analog, and mixed-signal ICs for broadband, connectivity, infrastructure, and industrial markets. It offers system-on-chip solutions for cable broadband, fiber-to-the-home networks, and Wi-Fi, plus RF transceivers and high-speed interconnects for data centers, set-top boxes, automotive video systems, and mobile devices. It is a fabless company that outsources manufacturing to foundries like UMC and targets OEM, ODM, and module makers, expanding its portfolio through acquisitions such as Exar, Intel’s Home Gateway Platform Division, and NanoSemi. Its goal is to provide scalable, high-quality semiconductor solutions that enable reliable connectivity across home, mobile, automotive, and data-center applications, while growing through diversified products and strategic acquisitions.

Company size
1,001-5,000
Company stage
IPO
Headquarters
Carlsbad, CA
Founded
2003

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