Senior Manager - SI Hardware

Job Description

<p><b>What to Expect</b>&#160;</p><p>Tesla is rapidly scaling its SI Hardware team in Bengaluru to design and verify next-generation custom silicon for accelerating machine learning workloads. These chips power Full Self-Driving (FSD), the Optimus humanoid robot, and Dojo supercomputing systems.&#160;</p><p>As the DV Lead in India, you will build and lead the Design Verification function for our growing Bengaluru site. You will own pre-silicon verification strategy for complex SoCs, drive high-quality tape-outs, mentor a team of DV engineers, and collaborate closely with global teams in Palo Alto and Austin. This is a foundational leadership role to establish Tesla&#8217;s first dedicated DV site in India, ensuring seamless integration with the global SI silicon roadmap.&#160;</p><p><br></p><p><br></p>&#10;&#10;

Job Responsibilities

What You’ll Do 

• Lead and Scale the DV team: Build, mentor, and grow the DV team in Bengaluru (from individual contributors to a high-performing site). Hire top talent, set technical direction, and establish best practices for UVM-based verification. 

• Own Verification Strategy: Architect and drive metric-driven, reusable SOC-level verification environments for SI accelerators, including block, subsystem, and full-chip verification. 

• Technical Ownership: 

• Develop coverage-driven verification plans from architecture specifications. 

• Architect highly reusable UVM testbenches, integrate complex VIPs (e.g., for NOC, PCIe, AXI, DDR, coherency), and achieve sign-off coverage targets. 

• Verify key SoC features: CPU/GPU integration, coherency protocols, memory subsystems, boot sequences, power/UPF, reset, HW/FW co-verification, and security. 

• Cross-Functional Collaboration: Partner with global RTL Design, Architecture, DFT, Emulation, Software/Firmware, and Post-Silicon teams to close verification gaps efficiently. 

• Emulation & Post-Silicon: Drive emulation (Palladium/Zebu) flows and support silicon bring-up/validation. 

• Process & Innovation: Improve verification methodologies, leverage AI-assisted tools, and ensure first-pass silicon success for Tesla’s cutting-edge SI chips. 

• Represent the DV team in global technical reviews, roadmap planning, and resource allocation. Drive knowledge transfer and alignment with US-based leads. 

Job Requirements

What You’ll Bring 

• Experience: 12+ years in ASIC/SoC Design Verification, with at least 4+ years in a technical leadership role (Lead/Manager/Architect) for complex multi-core SoCs or AI/GPU-like designs. 

• Expertise: 

• Deep hands-on experience with UVM/SystemVerilog, constrained-random verification, coverage closure, and assertion-based verification. 

• Strong background in SOC architecture: coherency, interconnects (AXI/AHB/NOC), high-speed interfaces (PCIe, DDR), memory controllers, multi-processor systems, and power management. 

• Experience with CPU/GPU integration, emulation platforms, and post-silicon bring-up. 

• Proficiency in scripting (Python, Perl, Tcl) and C/C++ for test development. 

• Leadership: Proven track record of building and leading DV teams, delivering multiple tape-outs, and mentoring engineers. Ability to attract and retain top semiconductor talent in India. 

• Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field (or equivalent experience). 

• Nice-to-Haves: 

• Prior experience on SI accelerators, NPUs, or high-performance computing chips. 

• Familiarity with formal verification, low-power verification (UPF), or security verification. 

• Experience working in global, distributed teams (US-India collaboration)