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Cadence Design Systems

Develops EDA software, IP, verification tools

Design Engineer 2

Hardware Validation & TestingConfirmed live in the last 24 hours
Full-timeNoida, Uttar Pradesh, IndiaNo salary listedIn-person

About the Job

Requirements

  • A B.Tech or M.Tech degree in Electronics and Communication Engineering (ECE) is required.
  • Experience with SystemVerilog, Universal Verification Methodology (UVM), and C/C++ for architectural modeling is required.
  • Experience with processor integration, such as RISC-V or ARM, and industry-standard protocols such as AMBA or PCIe is required.
  • Expertise in scripting with Perl, Python, or Tcl for verification flow automation is required.
  • A proven track record in verifying complex pipelines, memory subsystems, or instruction set architecture (ISA) implementations is required.

Responsibilities

  • Develop simulation testbenches in C, C++, or RTL and lead the development of reusable UVM environments.
  • Champion the integration of formal verification and AI-driven coverage analysis.
  • Partner with microarchitecture, RTL design, and software teams to align verification plans with ISA requirements.

About the Company

Cadence Design Systems

Develops EDA software, IP, verification tools

Cadence Design Systems supplies software, hardware, and IP for electronic design automation (EDA) to help customers create advanced semiconductor chips and electronic systems. Its tools handle system design, verification, digital and analog IC design, and custom flows, while IP such as Tensilica processors and DSP cores can be licensed for integration into customer products. The offerings are delivered as software licenses with maintenance and support, plus IP licensing and occasional hardware-accelerated options. The company differentiates itself with a broad, end-to-end EDA portfolio and close collaboration with industry leaders to streamline the path from concept to silicon, aiming to help customers bring sophisticated silicon and electronics to market faster with lower risk and higher productivity.

Company size
10,001+
Company stage
IPO
Headquarters
San Jose, CA
Founded
1988

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