Principal Systems Engineer - Automotive MCU

NXP Semiconductors stock: TD Cowen cuts target to USD 275.00. Published on 10/21/2026 at 16:37 | Editorial responsibility: Rafael Müller, Editor-in-Chief AD HOC NEWS TD Cowen cut its target from USD 290.00 to USD 275.00 on October 20, 2026. NXP Semiconductors stock costs EUR 213.25 on October 21, 2026. Target and earnings date. * TD Cowen lowered its NXP Semiconductors target from USD 290.00 to USD 275.00 on October 20, 2026. * NXP Semiconductors reported USD 3.50 billion in second-quarter 2026 revenue, up 19.50 percent year over year. * NXP Semiconductors stock costs EUR 213.25 at Lang & Schwarz on October 21, 2026 at 4:32 p.m. CEST. * Third-quarter 2026 results are scheduled for October 27, 2026. NXP Semiconductors (ISIN NL0009538784) is trading at EUR 213.25 at Lang & Schwarz on October 21, 2026 at 4:32 p.m. CEST. MarketBeat reported on October 20, 2026 that TD Cowen lowered its target from USD 290.00 to USD 275.00 while maintaining a Buy rating. Discover more Compare CPUs Track Stock Market TD Cowen lowers its target. The cut leaves TD Cowen's target 14.87 percent above the USD 239.40 Nasdaq price supplied for October 21, 2026. The target change is the clearest recent analyst adjustment in the coverage reviewed, while the rating remained Buy. The broader analyst picture is still divided. MarketBeat listed 16 Buy ratings, nine Holds and one Sell rating, with an average target of USD 304.26. That average is 27.06 percent above the USD 239.40 Nasdaq price, but the range between individual targets remains wide. Revenue reached USD 3.50 billion. NXP's second-quarter 2026 revenue was USD 3.50 billion, up 19.50 percent from USD 2.93 billion in the same quarter a year earlier, according to MarketBeat. The same report said quarterly earnings per share reached USD 3.61, beating the USD 3.52 consensus by USD 0.09. The latest standardized financial figures put second-quarter 2026 net income at USD 767.0 million and diluted earnings per share at USD 3.02. The differing earnings-per-share figures reflect different reporting definitions, so the adjusted result and the standardized figure are kept separate. Results arrive October 27. NXP Semiconductors announced on October 6, 2026 that it will publish third-quarter 2026 results after the Nasdaq close on October 27, 2026, followed by a conference call at 4:30 p.m. EDT. The date gives investors a defined checkpoint for testing demand in automotive, industrial and Internet of Things markets. The company reported USD 12.27 billion of revenue for fiscal year 2025, according to the same release. NXP's profile covers processing, connectivity, security, sensing and power-management solutions for automotive and industrial systems. Stock position and valuation. NXP Semiconductors has a market capitalization of USD 60.4 billion as of October 21, 2026. Its Nasdaq 52-week range is USD 183.00 to USD 339.95, while the price-to-earnings ratio is 20.42. The shares therefore remain below the yearly high, leaving the October 27 results as the next dated company event. Price stays at EUR 213.25. Discover more Source Parts Invest in Stocks The stock was trading at EUR 213.25 at Lang & Schwarz on October 21, 2026 at 4:32 p.m. CEST. On the Nasdaq, NXP Semiconductors was trading at USD 239.40 at 2:37 p.m. EDT on the same date. The two quotations are separate venue observations. The further course of trading is shown by the continuously updated real-time quote of NXP Semiconductors stock. NXP Semiconductors at a glance. * Company: NXP Semiconductors N.V. * ISIN: NL0009538784 * Ticker: NXPI * Primary exchange: Nasdaq * Price Lang & Schwarz (as of October 21, 2026, 4:32 p.m. CEST): EUR 213.25 * Market capitalization: USD 60.4 billion (as of October 21, 2026) * 52-week range: USD 183.00-USD 339.95 (as of October 21, 2026) * Sector / Industry: Technology / Semiconductors * Next earnings date: October 27, 2026 Sponsored Ad NXP Semiconductors stock: new analysis - 24 October. Fresh NXP Semiconductors information released. What's the impact for investors? Our latest independent report examines recent figures and market trends. Disclaimer regarding our articles: This is not investment advice, nor is it a recommendation to buy or sell. Information regarding prices, companies, and markets is provided without guarantee; changes may occur at any time. Stock market transactions can result in significant losses. Our articles are created and reviewed, in whole or in part, automatically with the assistance of AI. en | NL0009538784 | NXP SEMICONDUCTORS | boerse | 70385396 | bgmi

SEALSQ shows quantum-resistant chips at Munich's Electronica fair. SEALSQ will demonstrate two new quantum-resistant chips and a post-quantum ASIC design concept at electronica 2026, November 10-13 in Munich, positioning the company to influence the next generation of connected products before an expected audience of over 80,000 visitors. The company's presence at the world's leading electronics trade fair includes a roundtable discussion with NXP and Infineon focused on industrial security. "Electronica is where embedded decisions get made," said Gweltas Radenac, Product Marketing Director at SEALSQ. "We are bringing the chips and the live demos to Hall C6 so manufacturers can see what a quantum-ready Root of Trust looks like before they lock their next design." Secure Networks SEALSQ unveils quantum-resistant chips and QASIC at Electronica 2026. SEALSQ will showcase a functional quantum-computer mock-up at Electronica 2026, a tangible representation of the threat its new chips are designed to mitigate. Visitors will also see a quantum-computer mock-up, silicon quantum-computing partner. The exhibit runs from November 10-13, 2026, at the Trade Fair Center Messe Munich, a key venue attracting over 80,000 visitors. The company's new QASIC design concept represents a departure from traditional semiconductor development, according to David Fresneau, Strategic Marketing Director at IC'Alps. "At Electronica we are showing what QASIC truly represents: not another catalog chip, but a new approach to designing trusted custom semiconductors," he said. QASIC uses IC'Alps' expertise in analog, digital and mixed-signal ASIC design, functional safety, and ultra-low-power architectures, along with cybersecurity technologies and post-quantum cryptographic solutions. This collaboration enables the rapid development of application-specific semiconductors optimized for demanding markets like automotive, medical, industrial and critical infrastructure, prioritizing security, resilience and performance. The approach aims to streamline the creation of custom chips with built-in, future-proof security features. SEALSQ's participation extends beyond the exhibit hall, with a roundtable discussion scheduled for November 11th. Source Parts The event, "Physical AI at the Edge for Industrial Security," will feature representatives from NXP and Infineon, highlighting a collaborative effort to address security challenges in industrial applications. The company will also deliver a keynote presentation on November 13th at the Embedded Systems World Forum, focusing on simplifying the migration to post-quantum security standards through certified secure hardware, and its focus is on embedding certified secure hardware to simplify the transition to post-quantum security standards for manufacturers. Secure Networks Stay current See today's quantum computing news on Quantum Zeitgeist for the latest breakthroughs in qubits, hardware, algorithms, and industry deals.

NXP's P3B1602DP brings the industry's first I3C bus buffer to market. * October 14, 2026 * by Bob Gee As I3C adoption accelerates across next-generation computing and embedded systems, NXP recognized a critical infrastructure gap: designers needed a purpose-built buffer that could preserve I3C performance while supporting voltage translation, larger bus capacitance, and longer PCB traces. The new P3B1602DP addresses that need with a 2-bit I3C bus buffer supporting up to 12.5 MHz SDR and DDR operation, voltages as low as 0.72 V, and capacitive loads up to 100 pF. Interview with Bob Gee on the NXP P3B1602DP. Q1: NXP appears to be first-to-market with an I3C bus buffer. Why did NXP decide to develop this product? Bob Gee: NXP Semiconductors NV saw a clear need emerging as the industry transitions from I[2]C to I3C. New processors, SoCs, application processors, MCUs, and system controllers are increasingly adopting I3C because it provides significantly higher performance, greater efficiency, and better system scalability than legacy interfaces. As adoption increased, system designers began running into practical challenges. I3C buses are optimized for higher speeds and generally lower bus capacitance, but many real-world systems require longer PCB traces, connectors, multiple board-to-board links, or voltage translation between devices operating at different supply rails. What was missing from the market was a dedicated buffer designed specifically for I3C. NXP recognized that gap early and developed the P3B1602DP to help customers extend I3C buses without sacrificing the performance advantages that motivated their migration to I3C in the first place. The result is a device that combines buffering, bidirectional level translation, automatic direction sensing, and support for larger capacitive loads, making I3C easier to deploy in demanding system architectures. Q2: Modern processors continue to operate at lower voltages. How does the P3B1602DP address this challenge? Bob Gee: One of the key strengths of the P3B1602DP is its exceptionally wide and low voltage operating range. Port A supports supply voltages from 0.72 V to 1.98 V, while Port B supports 1.08 V to 3.63 V, allowing seamless communication between next-generation low-voltage controllers and higher-voltage peripheral devices. This is particularly important in modern AI servers, data center accelerators, networking equipment, robotics platforms, and telecom infrastructure. The latest SoCs and application processors often operate at core voltages around 0.8 V to 1.2 V, while attached sensors, power devices, DDR memory, and management ICs may operate at higher voltages. The P3B1602DP eliminates the need for designers to compromise between performance and interoperability. It allows customers to leverage the benefits of low-voltage silicon while maintaining compatibility across mixed-voltage systems through automatic bidirectional voltage-level translation. Q3: I3C is known for its speed. How does the P3B1602DP help maintain signal integrity at high bandwidths? Bob Gee: The promise of I3C is high bandwidth. The P3B1602DP fully supports I3C operation with data rates up to 12.5 MHz SDR and DDR, while also supporting legacy I[2]C and SMBus interfaces. However, high-speed operation alone is not enough. System designers frequently need to drive larger loads than a typical I3C bus was originally intended to support. That's where the P3B1602DP stands out. The device is designed to support up to 100 pF capacitive loading, which is double the allowable capacitance for an I3C bus. It also incorporates a longer one-shot accelerator pulse, specifically engineered to drive larger capacitive loads and compensate for longer signal propagation paths. In practical terms, this means customers can support: * Longer PCB traces * Larger backplanes * Board-to-board interconnects * Greater round-trip signal delays * Higher capacitive loading Without giving up the performance advantages of I3C. The datasheet specifically notes support for larger capacitive loads, longer round-trip delays, and PCB traces up to approximately 40 inches. For applications such as AI servers, accelerator cards, telecom line cards, industrial robotics, and advanced embedded computing, this capability can significantly simplify system-level design while maintaining reliable high-speed communication. Q4: Why is it important to use an industry-standard TSSOP8 package and pinout? Bob Gee: Ease of adoption was a major design goal. Engineers don't just evaluate electrical performance; they also consider how quickly a device can be integrated into existing hardware platforms. The P3B1602DP is offered in an industry-standard TSSOP8 package with a familiar pinout and a compact 3 mm x 3 mm footprint. This allows customers to adopt the device with minimal layout disruption and often reuse existing design practices and manufacturing processes. Just as importantly, the device is specified across a-40°C to +125°C temperature range, making it suitable for environments that require industrial and infrastructure-grade robustness. This combination of standard packaging, broad voltage support, high-speed I3C capability, and extended temperature operation make it an attractive solution for: * AI data centers * Enterprise servers * Telecom infrastructure * Industrial automation * Robotics platforms * Edge computing equipment Ultimately, NXP Semiconductors NV wanted customers to benefit from cutting-edge I3C performance without introducing unnecessary adoption barriers, and the standard TSSOP8 footprint helps accomplish exactly that. Closing thoughts. Bob Gee: The P3B1602DP demonstrates NXP's commitment to enabling the next generation of system architecture. By being first to address the emerging need for an I3C-specific buffer, NXP has created a solution that combines ultra-low-voltage support, high-speed I3C performance up to 12.5 MHz, robust 100 pF drive capability for longer signal paths, and an industry-standard TSSOP8 package that simplifies implementation across data center, server, robotics, industrial, and telecom applications. Product Marketing Director of General Purpose and High Speed Interface Products at NXP Semiconductors He has more than 30 years of technical marketing experience in multi-market applications and electronic distributor business. He is currently focused on general purpose I/O expanders, voltage level translators, high speed interface, and legacy analog devices. He graduated with a BSEE from University of Massachusetts at Amherst and currently lives in Sunnyvale California.