Physical Design Engineer

Summary

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Minimum Qualifications

Bachelors degree or foreign equivalent in Electronics Engineering, Electrical Engineering, Computer Engineering, or related field. Experience and/or education must include: Using Cadence Innovus, Synopsys ICC-2 to work on Place and Route of complex digital logic blocks. Using Primetime-SI to analyze timing results and generate fixes needed. Using Calibre to understand and debug physical verification results including LVS, DRC and antenna checks. Utilizing UPF and knowledge of Conformal-LP to verify low power intent. Using Voltus, Redhawk to generate EM and IR results to analyze the power-grid integrity. Ability to generate fixes based on violations reported. Utilizing TCL, Python, TCSH to develop automation scripts that improve efficiency. Using Innovus CCOPT to analyze and optimize clock-tree to minimize power, improve latency and skew. Leveraging semiconductor device physics to make informed power, performance, and area (PPA) trade-offs in PnR implementations. Using Verilog for design and verification, and ability to write Verilog modules. Leveraging microprocessor system design, including architecture, datapath, control logic, and memory hierarchy.

Preferred Qualifications

N/A

Description

APPLE INC has the following available in Beaverton, Oregon. Physical Design implementation of partitions and develop/test place and route flows. Implement physical design of partitions and top level. Develop and test place and route flows. Conduct floor planning, pin assignments, macro placement and evaluation of logic. Iterate over placement to get the optimized placement and timing. Clock tree synthesis, optimization, routing and post-route optimization. Conduct setup, hold, transition and other static timing checks and closure. Run Static Voltage Droop and dynamic Voltage Droop and other power related optimization and signoff. Conduct formal checking and signoff, full chip timing closure, physical verification and closure, and signoff checklist closure. 40 hours/week.