SoC Physical Design Engineer - Multiple Teams

Summary

Imagine what you could do here. At Apple, new ideas have a way of becoming great products very quickly. Do you want to bring passion and dedication to your job? There's no telling what you could accomplish at Apple. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices — we continue to strengthen our commitment to leave the world better than we found it. By now the industry is accustomed to Apple taping out the SoCs for our various products at a rigorous pace. In order to achieve this our world-class design processes are driven by our top-notch Physical Design engineers. Are you a classic partition PnR engineer recognised in the industry for the knowledge in standards and practices in Physical Design? Do you have strong track record with recent successful tape-outs in deep sub-micron technology? As SoC Digital Physical Design Engineer, you will take part in the large scale SoC physical design cycle from netlist to tape-out, including full flow of back-end implementation and verification always meeting schedule and design goals. Are you ready to join some of the world's leading engineers and help us deliver the next generation of ground-breaking Apple products? Join Us!

Minimum Qualifications

You hold a MSEE or equivalent strong experience. We will be counting on your expertise and years of hands on experience with one of the Place & Route ('PnR') tools available today (Synopsys / Cadence), and having understanding of their capabilities and underlying algorithms. You can do scripting and programming using several of the following: Perl, TCL and Make.

Preferred Qualifications

We expect experience with large SoC designs (>20M gates) with frequencies in excess of 1GHZ and beyond. If you also have working knowledge in Verilog, that is a huge plus for us. Your communication skills are excellent, and like the rest of us here at Apple you love working in open and multi-cultural environment. You are familiar with hierarchical design approach, top-down design, and timing and physical convergence. You are demonstrating in-depth understanding of static-timing analysis, extensive know-how in clock/power distribution and analysis, as well as RC extraction and correlation. You have experience with SoC practices such as multiple voltage and clock domains, integration of mixed-signal IPs and I/O integration.

Description

You are going to own block level PnR, floor-planning, clock and power distribution You will get involved with static timing closure with commercial tools You will do power & noise analysis (EM/IR-Drop/Xtalk) as well as layout verification (DRC/LVS) You will be developing and validating dedication low power clock network guidelines With phenomenal focus you will resolve design and flow issues related to physical design and identify potential solutions whilst driving execution You know what documentation should look like, and will help with guidelines and specs

Responsibilities

As a member of our Physical Design team in this highly transparent role, you will directly own implementation of design partition(s) (Netlist to delivery of our final GDS) for a highly complex SoC using brand-new process technology