Cadence Design Systems

Develops EDA software, IP, verification tools

Senior Design Engineering Architect

Silicon & ASIC DesignConfirmed live in the last 24 hours

Full-timeBengaluru, Karnataka, IndiaNo salary listed

About the Job

Requirements

A BE, BTech, ME, or MTech degree in Electrical, Electronics, or VLSI is required.
Experience as a design and verification engineer, with a large portion of recent work focused on RTL design and development, is required.
Six to sixteen years of core RTL design experience using Verilog is required.
Experience with SystemVerilog and using or debugging a Universal Verification Methodology-based environment is required.
Experience architecting and designing CPU subsystems, including memory, input/output, and cache subsystems, is required.

Responsibilities

Develop RTL for Interface Controller intellectual property.
Architect PCIe solutions with ARM CPU subsystems, including memory, input/output, and cache subsystems.
Design and support RTL for PCIe, CXL, IDE, and UALink intellectual property solutions.
Add new features to RTL and work with existing RTL.
Ensure customer configurations are clean as part of verification regressions.
Support customers.
Ensure the design complies with LINT and clock-domain-crossing design guidelines.

Desired Qualifications

Experience with PCIe, CXL, and IDE.
Prior experience implementing complex protocols.
Prior experience in IP development teams.
Knowledge of scripting.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Position Description:

RTL Design Engineer for Interface Controller IP development team.
Position is based in Bangalore or Noida.
The role is for PCIe Architect with ARM CPU subsystem architecture, including memory subsystem design, IO and cache subsystems.
The role would also include design and support of the RTL of the PCIe/CXL/IDE/UALink IP solution of Cadence.
The work involved will be addition of new features into the RTL, working with existing RTL, ensuring various customer configurations are clean as part of verification regressions, supporting customers, ensuring design is clean for LINT and CDC design guidelines.

Position Requirements:

BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer, with a large portion of the recent work experience on RTL design and development.
6-16 years of core RTL Design experience using Verilog is a must.
System Verilog experience and experience with UVM based environment usage / debugging is required.
Architecture and design of CPU subsystem, including memory subsystem design, IO and cache subsystems is a must.
PCIe/CXL/IDE experience is highly desirable. Prior experience in implementation of complex protocols is desirable.
Prior experience in IP development teams would be an added advantage.
Scripting knowledge is an advantage.

We’re doing work that matters. Help us solve what others can’t.

About the Company

Cadence Design Systems

Develops EDA software, IP, verification tools

Cadence Design Systems supplies software, hardware, and IP for electronic design automation (EDA) to help customers create advanced semiconductor chips and electronic systems. Its tools handle system design, verification, digital and analog IC design, and custom flows, while IP such as Tensilica processors and DSP cores can be licensed for integration into customer products. The offerings are delivered as software licenses with maintenance and support, plus IP licensing and occasional hardware-accelerated options. The company differentiates itself with a broad, end-to-end EDA portfolio and close collaboration with industry leaders to streamline the path from concept to silicon, aiming to help customers bring sophisticated silicon and electronics to market faster with lower risk and higher productivity.

Company size: 10,001+
Company stage: IPO
Headquarters: San Jose, CA
Founded: 1988

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