Fundamental IP Design Kit and Characterization Manager - ASICS Engineering

Company:

Qualcomm Semiconductor Limited

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

Job Overview

Lead and contribute to the development, design-kit, modeling, characterization, and delivery of high-performance IP blocks (I/O, memory, standard cell libraries) for advanced CMOS/FinFET technology nodes. Collaborate across global teams to define methodologies, flows, and design-kits supporting Qualcomm’s mobile, automotive, IoT, and consumer products.

Key Responsibilities

• Lead the end-to-end development of IP blocks and SoCs, including documentation, modeling (digital and analog), optimization and verifications.
• Lead to deliver design-kits including behavioral and timing models for I/Os, memories, and standard cell libraries.
• Oversee the development of RTL models in Verilog/SystemVerilog, including creating comprehensive verification plans and validating both behavioral and transistor-level implementations.
• Develop and automate characterization flows using scripting languages (Python, Perl, TCL).
• Drive methodology and flow improvements with internal and external tool vendors.
• Support SoC teams throughout the design cycle; debug issues at IP and SoC levels.
• Collaborate with cross-functional teams (software, hardware, product/program management) to meet system and customer requirements.
• Write and review detailed technical documentation for EDA/IP/ASIC projects.
• Supervise and mentor junior engineers; provide guidance and influence key organizational decisions.

Minimum Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• Have Standard cell / Memory/IO circuit knowledge & design-kit & IP characterization background.
• 6+ years of ASIC design, verification, validation, integration, or related work experience (Manager level).
• Solid knowledge of CMOS, FinFET logic, transistor fundamentals, and digital circuit design optimization.
• Experience in IP characterization, design-kit delivery, and EDA tool automation.
• Strong programming skills in Python, Perl, or TCL on UNIX/Linux platforms.
• Hands-on experience with Liberty formats (NLDM, CCS, LVF), statistical variation models, and design kit views.
• Familiarity with RTL design/coding, logic design, verification, SystemVerilog Assertions (SVA), DFT, BIST modeling.
• Experience with static timing analysis (STA), physical design, and spice simulation models.
• Excellent analytical, debugging, and problem-solving skills.
• Highly motivated, strong team spirit, and effective communication skills.

Preferred Qualifications

• Master’s degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.
• 9+ years of relevant experience.
• 3+ years with architecture/design tools, scripting/programming languages, and design verification methods.
• Experience interacting with senior leadership.
• Prior experience in analog/mixed-signal simulations and commercial characterization tools.
• Ability to work in multi-site project teams and with third-party vendors.

What Makes You Stand Out

• Expertise in large-scale software automation, data analysis, and visualization.
• Experience developing automation from scratch for characterization flows and sign-off methodologies.
• Silicon reliability modeling and validation with multiple foundries and EDA houses.
• Exposure to RTL to GDSII flow and advanced chip design tools (Virtuoso, Synthesis, DFT, Power Analysis).

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

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