Cadence Design Systems

Develops EDA software, IP, verification tools

IC Design Implementation and Signoff Architect - STA Signoff

Silicon & ASIC DesignConfirmed live in the last 24 hours

Full-timeIn-person

About the Job

Requirements

At least 15 years of experience in IC design implementation and signoff, with demonstrated success managing large-scale technical programs.
Deep expertise in digital design fundamentals, advanced-node static timing analysis and engineering change orders at 3 nm and below, and electronic design automation tool ecosystems.
Core timing signoff expertise, advanced-node static timing analysis, Unified Power Format and constraints debugging, hierarchical and 3D integrated-circuit design static timing analysis, and closure solutions.
A proven track record of leading technical teams and driving customer success at executive levels.
Strong proficiency in Tcl, Python, Perl, and flow customization for design closure.
A Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.

Responsibilities

Lead technical engagements with customers and partners to drive adoption of Cadence’s signoff portfolio.
Work closely with design teams to meet customer success metrics and guide adoption of Cadence timing signoff and closure and AgenticAI features across advanced nodes of 5 nm and below.
Partner with research and development and Product Engineering to influence tool enhancements based on real-world customer requirements.
Drive complex benchmarks, flow optimizations, and deployment of cutting-edge methodologies for timing signoff and closure, static timing analysis, IR drop, and power and timing closure.
Represent Cadence at industry forums, author technical papers, and deliver keynote presentations to position Cadence as a market leader.

Desired Qualifications

Prior experience with Cadence tools (Tempus, Certus, QRC) and competitive solutions is highly desirable.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Key Responsibilities

Technical Expertise: Lead technical engagements with customers and partners to drive & adoption of Cadence signoff portfolio. Work closely with design teams to meet customer success metrics, guide adoption of Cadence’s timing signoff & closure and AgenticAI features across advanced nodes (5nm and below).
Cross-Functional Collaboration: Partner with R&D and Product Engineering to influence tool enhancements based on real-world customer requirements.
Innovation & Enablement: Drive complex benchmarks, flow optimizations, and deployment of cutting-edge methodologies for timing signoff & closure, STA, IR Drop, and power/timing closure.
Thought Leadership: Represent Cadence at industry forums, author technical papers, and deliver keynote presentations to position Cadence as a market leader.

Requirements

15+ years of experience in IC design implementation and signoff, with demonstrated success in managing large-scale technical programs.
Deep expertise in digital design fundamentals, advanced node STA & ECOs (3nm and below), and EDA tool ecosystems.
Core timing signoff expertise, advanced node STA, UPF & constraints debugging, hierarchical & 3DIC design STA and closure solutions
Proven track record of leading technical teams and driving customer success at executive levels.
Strong proficiency in scripting (Tcl, Python, Perl) and flow customization for design closure.
Excellent communication, negotiation, and leadership skills with the ability to influence internal and external stakeholders.
Prior experience with Cadence tools (Tempus, Certus, QRC) and competitive solutions highly desirable.
BS/MS in Electrical Engineering, Computer Engineering, or related field

The annual salary range for Washington is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure.Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

We welcome applications from candidates with disabilities and in equity seeking groups. If you have accessibility needs during the application and interview process, we encourage you to make your needs known.

About the Company

Cadence Design Systems

Develops EDA software, IP, verification tools

Cadence Design Systems supplies software, hardware, and IP for electronic design automation (EDA) to help customers create advanced semiconductor chips and electronic systems. Its tools handle system design, verification, digital and analog IC design, and custom flows, while IP such as Tensilica processors and DSP cores can be licensed for integration into customer products. The offerings are delivered as software licenses with maintenance and support, plus IP licensing and occasional hardware-accelerated options. The company differentiates itself with a broad, end-to-end EDA portfolio and close collaboration with industry leaders to streamline the path from concept to silicon, aiming to help customers bring sophisticated silicon and electronics to market faster with lower risk and higher productivity.

Company size: 10,001+
Company stage: IPO
Headquarters: San Jose, CA
Founded: 1988

Recently Posted Jobs

Explore more opportunities at Cadence Design Systems

See more jobs