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Cadence Design Systems

Develops EDA software, IP, verification tools

Application Engineer 1: Physical Design - Synthesis and Digital Implementation

Silicon & ASIC DesignConfirmed live in the last 24 hours
Full-timeBelo Horizonte, State of Minas Gerais, BrazilNo salary listedIn-person

About the Job

Requirements

  • Complete a Bachelor's degree in Electrical/Electronics or a related field.
  • Have exposure to CMOS fundamentals, digital electronics, and process technologies.
  • Have a basic understanding of scripting languages such as Perl, Tcl, or Python.
  • Have excellent debugging and analytical skills.

Responsibilities

  • Help customers enhance their productivity, debug complex issues, and provide solutions in digital tools and flows.
  • Establish technical credibility and rapport with customers and research and development.
  • Create high-impact knowledge content, tool adoption kits, and other high-level documents to increase customer self-service.
  • Produce out-of-the-box solutions to customer problems using tool capabilities or scripting techniques.

Desired Qualifications

  • Exposure to physical design is an added advantage.
  • Exposure to Cadence digital tools is a plus.

About the Company

Cadence Design Systems

Develops EDA software, IP, verification tools

Cadence Design Systems supplies software, hardware, and IP for electronic design automation (EDA) to help customers create advanced semiconductor chips and electronic systems. Its tools handle system design, verification, digital and analog IC design, and custom flows, while IP such as Tensilica processors and DSP cores can be licensed for integration into customer products. The offerings are delivered as software licenses with maintenance and support, plus IP licensing and occasional hardware-accelerated options. The company differentiates itself with a broad, end-to-end EDA portfolio and close collaboration with industry leaders to streamline the path from concept to silicon, aiming to help customers bring sophisticated silicon and electronics to market faster with lower risk and higher productivity.

Company size
10,001+
Company stage
IPO
Headquarters
San Jose, CA
Founded
1988

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