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Kandou AI

Provides chip-to-chip AI connectivity solutions

Analog Design Engineer

Silicon & ASIC DesignConfirmed live in the last 24 hours
Full-timeSaint-Sulpice, SwitzerlandNo salary listedHybrid

About the Job

Requirements

  • Deep understanding of design and layout techniques for high-speed and high-precision circuits.
  • Experience developing testbenches and simulation setups to analyze circuit and system performance.
  • Skill in layout techniques, including matching, parasitic estimation and reduction, and deep-submicron-related issues.
  • Advanced proficiency with electronic design automation tools for design and verification, preferably Cadence Virtuoso, Spectre/HSpice, Calibre/PVS DRC/LVS, parasitic extraction and modeling, electromagnetic and IR-drop tools, and ESD analysis.
  • At least 5 years of experience designing and laying out analog and mixed-signal circuits, especially high-speed and high-precision circuits, such as multi-gigabit serial data-link transceivers, RF circuits, equalizers, clock generators, PLLs, clock and data recovery circuits, ADC or DAC data converters, biasing circuits, and bandgap circuits.
  • MSc or PhD in electronics or electrical engineering, or equivalent or higher.
  • Experience with modern semiconductor process technologies such as CMOS 28nm and FinFET 16/14nm and 7nm.
  • Experience in high-level modeling, top-level simulations, and signal integrity.
  • Solid background in signal processing and communications.
  • Ability to manage workload and schedules and report to internal management and technical teams.

Responsibilities

  • Develop block-level specifications and models for target designs.
  • Develop, model, design, and verify the performance of custom analog circuits in advanced technology nodes.
  • Design and develop layouts, including floor-planning, guiding layout engineers, and post-layout verification.
  • Verify designs at different levels, including pre- and post-layout and variation-aware verification.
  • Support and collaborate with the design team, including design and layout engineers, architects, chip-level integration engineers, modeling specialists, and system-level designers.
  • Support post-silicon laboratory bring-up, debugging, characterization, and productization.
  • Produce progress, analysis, design, modeling, and verification reports.
  • Participate in developing concept-level architectures and circuits.

Desired Qualifications

  • Problem-solving and analytical skills.
  • Self-motivation and a strong sense of ownership and responsibility.
  • Communication and reporting skills.
  • Cadence Virtuoso, Spectre/HSpice, Calibre/PVS DRC/LVS, parasitic extraction and modeling, electromagnetic and IR-drop tools, and ESD analysis are preferred.

About the Company

Kandou AI

Provides chip-to-chip AI connectivity solutions

Kandou AI designs and sells semiconductor connectivity hardware for AI workloads. It provides a memory fabric and CXL controllers that link processors to memory, enabling scalable, energy-efficient AI inference and training clusters built from affordable hardware. Using Copper MIMO interconnect, it reduces energy per bit and supports features like offloading AI training collectives, switchless memory for in-memory databases, and field-repairable co-packaged optics for better cooling. By targeting the data-movement bottleneck between processors and memory and offering chiplet-based fabrics and IP licensing, Kandou AI aims to make scalable AI infrastructure more accessible to hyperscalers, data centers, and system integrators.

Company size
201-500
Company stage
Late Stage VC
Total funding
$504.7M
Headquarters
Lausanne, Switzerland
Founded
2011

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