Design Verification Engineer

Summary

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Minimum Qualifications

Master's degree or foreign equivalent in Electrical and Computer Engineering, Electrical Engineering, or related field. Experience and/or education must include: Using hardware description languages including Verilog and VHDL to develop digital designs Using hardware programming language System Verilog develop test benches for digital designs including reference models, stimulus generation and debugging design under test Writing programs and designing system models that need object oriented programming approach using programming languages including C/C++ Using combinational and sequential circuit designs and their usage patterns to understand, verify and debug digital designs Understanding of Microprocessors architecture, processor organization, instruction set architecture and assembly instructions to work on microprocessor design verification, integration Understanding of CPU architecture in relation to multi-threading, interrupt handling, semaphores and how these features are used in SoCs Using Linux/Unix operating systems to manage files, run commands, monitor jobs Using scripting languages including Perl, Bash and Python to work on automating jobs and write programs that can help in verification flows Using Industry Standard Tools including Cadence, Synopsys simulators to design digital blocks, simulate test benches and debug waveforms

Preferred Qualifications

N/A

Description

APPLE INC has the following available in Austin, Texas. Understand details of High-Efficiency SOC Architecture, standard SOC peripherals such as SPI, I2C, UART, Timer, DMA, memory management schemes, low power spec, multi-processor systems, DDR, PCIe, DDR, Memory Controller Sub Systems, USB, PLL, power-up, Secured Boot schemes. Create coverage driven verification plans from specifications, review and refine to achieve coverage targets. Create IP level module and sub-system verification plan, TB, portable test benches, sequences, and test infrastructure. Architect UVM-based highly reusable test benches and integrating complex multi-instance VIPs, sub-system test benches, and test suites to SOC level, achieve targeted coverage, working with design, architecture, SW, FW, and external IP delivery teams to efficiently integrate and verify overall SOC design. Collaborate closely with DV methodology architects to improve verification flow. 40 hours/week.