Q

Qualcomm

Designs mobile chips and licenses wireless patents

CPU Static Timing Analysis Engineer - Hardware Engineering

Silicon & ASIC DesignConfirmed live in the last 24 hours
Full-timeBengaluru, Karnataka, IndiaNo salary listedIn-person

About the Job

Requirements

  • A Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field and at least 2 years of Hardware Engineering or related work experience; alternatively, a Master's degree in those fields and at least 1 year of related work experience, or a PhD in those fields.
  • Strong experience with static timing analysis and timing closure for high-performance CPU or processor-class system-on-chip designs.
  • Expertise in multi-clock, multi-domain CPU designs with aggressive frequency targets.
  • Experience in deep sub-micron technology nodes and advanced process technologies.
  • Experience performing static timing analysis on large CPU/system-on-chip designs with multi-scenario and signoff-quality closure.
  • Hands-on knowledge of timing engineering change order techniques and their implementation for CPU frequency closure.
  • Understanding of standard cell libraries, CPU-critical path optimization, and timing trade-offs.
  • Familiarity with circuit modeling, transistor fundamentals, and worst-case corner selection for CPU timing signoff.
  • Understanding of industry-standard synthesis, place-and-route, and tape-out flows.
  • Knowledge of timing effects such as noise, cross-talk, on-chip variation, and their impact on CPU designs.
  • Working knowledge of CPU/system-on-chip architecture and hardware description languages such as Verilog.

Responsibilities

  • Work with CPU microarchitecture, RTL, and design-for-test teams to understand CPU pipelines, critical paths, and performance goals, and define, implement, and validate timing constraints.
  • Perform static timing analysis for high-performance CPU designs at block, cluster, and system-on-chip/top-level hierarchies across multiple modes, corners, and scenarios.
  • Analyze timing on frequency-critical CPU paths, including core, cache, interconnect, and clocking, and collaborate with RTL and design-for-test teams to drive logic and microarchitectural fixes.
  • Provide actionable timing feedback to block-level and top-level physical design engineers to enable CPU frequency and timing closure.
  • Partner with computer-aided design and methodology teams to develop, deploy, and enhance CPU-specific timing flows and infrastructure.
  • Generate and review logic and physical timing engineering change orders to close setup, hold, noise, and cross-talk violations in CPU designs.
  • Contribute to CPU timing methodology definition, best practices, and documentation for consistent signoff quality.

Desired Qualifications

  • A Master's degree in Electrical Engineering with at least 3 years of hands-on experience in static timing analysis and timing closure.
  • Excellent communication skills to work effectively with CPU architects, RTL designers, physical design, and computer-aided design teams.

About the Company

Qualcomm

Designs mobile chips and licenses wireless patents

Qualcomm designs the Snapdragon processors and modems inside many Android phones, and it licenses its wireless patents to device makers around the world. It helped commercialize CDMA, the cellular technology behind 3G networks, and its patents cover core parts of the 4G and 5G standards that phones use to connect. The company does not run its own chip factories; contract foundries make its chips, which it sells to makers of phones, PCs, cars, and connected devices. Device makers also pay Qualcomm royalties for using its patented technology, which forms a second business alongside chip sales. Qualcomm was founded in 1985 and is based in San Diego, California.

Company size
10,001+
Company stage
IPO
Headquarters
San Diego, CA
Founded
1985

Recently Posted Jobs

Explore more opportunities at Qualcomm

See more jobs