Wireless Design Verification Engineer

Summary

Would you like to join Apple’s growing wireless silicon development team? Our wireless SoC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Design Verification, Emulation, Test and Validation, and FW/SW engineering.

Minimum Qualifications

Minimum requirement of a bachelor's degree.

Preferred Qualifications

3+ years of verification experience of wireless/wired communication block/subsystem. Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion. Knowledge and experience of ASIC verification flows including test bench development, constrained random testing, and code/functional coverage. Verification experience of one or more of the following: MAC, PHY, DMA, timer, AMBA bus and fabric, encryption/decryption engine. Verification experience of wireless/wired communication block/subsystem. Knowledge of wireless protocols such as Bluetooth, UWB, WLAN, or Zigbee. Proficient in shell and Python scripting, Perl scripting. Experience of using AI technologies in data mining/analysis. Experience of Palladium/FPGA validation. Should be a team player with excellent communication skills, self-motivated and well organized.

Description

In this highly visible role, you will be at the center of a silicon design group with a critical impact on delivering world-class silicon to empower wireless products for hundreds of millions of customers. As a Wireless Design Verification Engineer, you will be responsible for pre-silicon RTL verification of wireless MAC and its interfaces with the rest of the wireless SoC. You will interact with DV methodologists, designers, and communication systems engineers to develop reusable testbench and verification environment deploying the latest methodology with metric-driven verification, ensuring the highest design quality.

Responsibilities

Work closely with the system and design teams to review and understand the MAC subsystem microarchitecture, and create verification plan from specification, review and refine to achieve coverage targets. Build block/subsystem level testbenches, create UVM libraries, using the best-in-class DV methodology. Architect test benches with maximum reusability in mind. Develop and execute both directed and constrained random tests, debug failures, manage bug tracking, and work with designers to drive closure of issues found. Create and analyze block/subsystem-level coverage models, and add test cases to increase coverage. Use machine learning and AI technologies to identify design and test bench issues and ensure DV quality. Support MAC subsystem validation using Palladium and/or FPGA. Work with team members to improve DV methodology and flow.