Advanced Packaging Technology & Integration Leader

Who We Are

Applied Materials is the global leader in materials science and engineering solutions that are at the foundation of virtually every new semiconductor chip and advanced display in the world. The equipment that we create and service is essential to advancing AI and accelerating the commercialization of next-generation semiconductor chips. Join us and push the boundaries of materials science and engineering in a company at the foundation of the electronics industry. The work we do together advances the world’s technology.

What We Offer

Salary:

$200,000.00 - $275,000.00

Location:

Santa Clara,CA

You’ll benefit from a supportive work culture that encourages you to learn, develop, and grow your career as you take on challenges and drive innovative solutions for our customers. We empower our team to push the boundaries of what is possible—while learning every day in a supportive leading global company. Visit our Careers website to learn more. 

At Applied Materials, we care about the health and wellbeing of our employees. We’re committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits. 

Position Summary

We are seeking an exceptional Advanced Packaging Technology & Integration Leader to lead the development of next-generation semiconductor packaging and 3D integration technologies.

This individual will combine deep technical expertise, first-principles problem solving, semiconductor process integration, and technical leadership. The successful candidate will have a demonstrated history of developing new technologies by understanding the fundamental physics, materials, interfaces, processes, and integration constraints rather than simply optimizing established process flows.

The role requires broad expertise across hybrid bonding, through-silicon vias (TSVs), advanced thermal materials and thermal management, interposers, bridge-die technologies, and heterogeneous integration. The individual will lead cross-functional teams spanning materials, unit-process development, integration, device/package architecture, modeling, characterization, equipment, and manufacturing.

Key Responsibilities

Technology Innovation & Pathfinding

• Develop differentiated semiconductor packaging technologies from first principles, translating fundamental understanding of materials, interfaces, mechanics, thermals, electrical performance, and process physics into practical technology solutions.
• Identify critical technology limitations in future AI/HPC, memory, and heterogeneous-integration architectures and develop new approaches to overcome them.
• Convert early concepts into experimentally testable structures, integration flows, and technology demonstrations.
• Establish technology roadmaps connecting future device and package requirements to new materials, processes, equipment capabilities, and integration schemes.
• Evaluate competing technical approaches and make clear recommendations based on fundamental engineering trade-offs.

Advanced Packaging Expertise Provide technical leadership across areas including:

• Wafer-to-wafer and die-to-wafer hybrid bonding
• Cu-Cu and dielectric bonding interfaces
• Bond-pad scaling, planarity, surface preparation, overlay, and alignment
• TSV formation and integration, including via etch, liner/barrier/seed, fill, reveal, stress, and wafer-thickness considerations
• 2.5D and 3D integration
• Silicon and alternative interposers
• Bridge-die architectures and integration
• Chiplets and heterogeneous integration
• Advanced redistribution and high-density interconnects
• Thermal materials and thermal-management integration
• Backside and embedded thermal-management concepts
• Warpage, stress, thermal-mechanical reliability, and interface engineering

Semiconductor Process Integration

• Develop complete process-integration strategies rather than isolated unit processes.
• Understand interactions among deposition, etch, CMP, cleans, bonding, lithography, metallization, wafer thinning, and packaging operations.
• Define integration experiments and learning cycles that identify root causes and fundamental process limitations.
• Work across process modules to understand trade-offs involving thermal budget, contamination, stress, topology, alignment, electrical performance, yield, and reliability.
• Drive technology from concept → proof of principle → integrated demonstration → manufacturable solution.

Technical Leadership

• Lead multidisciplinary teams of process engineers, integration engineers, materials scientists, modeling engineers, equipment engineers, and external collaborators.
• Establish the technical direction while giving teams sufficient freedom to explore unconventional solutions.
• Mentor senior technical staff and develop future technical leaders.
• Create an environment where hypotheses are challenged through physics, modeling, data, and experimentation.
• Lead technical reviews and clearly articulate complex technical issues to both engineering teams and senior executives.

Customer & Industry Engagement

• Engage with leading logic, memory, foundry, OSAT, and AI/HPC customers to understand future integration challenges.
• Translate customer architecture and scaling requirements into technology-development programs.
• Collaborate with universities, research organizations, material suppliers, equipment partners, and ecosystem companies where appropriate.
• Represent the organization as a technical authority in advanced packaging and heterogeneous integration.

Required Qualifications

• Advanced degree in Materials Science, Chemical Engineering, Electrical Engineering, Mechanical Engineering, Applied Physics, or a closely related discipline preferred, or equivalent demonstrated semiconductor technology-development expertise.
• Demonstrated experience developing semiconductor technologies or integration schemes from early concept through experimental validation.
• Deep understanding of semiconductor process integration.
• Strong expertise in several of the following, with broad understanding across the remainder:
  • Hybrid bonding
  • TSV technology
  • 2.5D/3D integration
  • Interposers
  • Bridge die
  • Chiplet integration
  • Thermal-management materials
  • Thin-wafer processing
  • Wafer/die bonding
  • Advanced metallization
  • CMP and surface preparation
  • Mechanical stress and wafer warpage
  • Semiconductor/package reliability
• Ability to reason from fundamental physics and materials behavior when established solutions are insufficient.
• Demonstrated ability to define experiments that distinguish between competing physical mechanisms and accelerate technical learning.
• Strong record of leading complex, multidisciplinary semiconductor technology-development programs.
• Demonstrated ability to mentor technical teams and influence organizations beyond direct reporting relationships.
• Excellent written and verbal communication skills, with the ability to communicate effectively from detailed engineering reviews through executive-level technology strategy.

Preferred Qualifications

• Experience developing technology for AI/HPC, HBM, chiplets, logic-memory integration, or other high-performance heterogeneous systems.
• Experience working across the semiconductor ecosystem, including device manufacturers, foundries, OSATs, equipment companies, material suppliers, or research organizations.
• Experience translating future device/package architectures into semiconductor process and equipment requirements.
• Track record of technical innovation demonstrated through patents, publications, technology transfers, or successful product/process introductions.
• Strong understanding of the interaction between electrical performance, power delivery, thermal management, mechanical integrity, manufacturability, cost, and yield.
• Experience moving technology across the transition from pathfinding/R&D into product development or manufacturing.

What Will Differentiate the Ideal Candidate

The strongest candidate will not simply be an expert in existing advanced-packaging processes.

We are looking for someone who can look at a problem such as hybrid-bond pitch scaling, thermal resistance, TSV stress, interposer complexity, or die-to-die integration and ask:

What is fundamentally limiting us, what physics governs that limitation, and what new technology could remove it?

They should then be capable of turning that insight into a technical hypothesis, designing the experiments needed to test it, building an integration strategy around it, and leading a team through development of a manufacturable technology.

Additional Information

Time Type:

Full time

Employee Type:

Assignee / Regular

Travel:

Yes, 10% of the Time

Relocation Eligible:

Yes

The salary offered to a selected candidate will be based on multiple factors including location, hire grade, job-related knowledge, skills, experience, and with consideration of internal equity of our current team members. In addition to a comprehensive benefits package, candidates may be eligible for other forms of compensation such as participation in a bonus and a stock award program, as applicable.

For all sales roles, the posted salary range is the Target Total Cash (TTC) range for the role, which is the sum of base salary and target bonus amount at 100% goal achievement.

Applied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.

In addition, Applied endeavors to make our careers site accessible to all users. If you would like to contact us regarding accessibility of our website or need assistance completing the application process, please contact us via e-mail at [email protected], or by calling our HR Direct Help Line at 877-612-7547, option 1, and following the prompts to speak to an HR Advisor. This contact is for accommodation requests only and cannot be used to inquire about the status of applications.