CAD Engineer - EMIR Signoff

Summary

Do you love building elegant solutions to highly complex challenges? Do you believe every detail matters? As part of our Silicon Technologies group, you’ll help design and manufacture Apple’s next-generation, high-performance, power-efficient system-on-chip (SoC) processors — the technology that lets Apple products and services handle everything our customers love doing with their devices, seamlessly and efficiently.

Minimum Qualifications

Minimum requirement of BS and 10+ years of relevant industry experience

Preferred Qualifications

Experience in CAD, EMIR analysis, or related circuit design roles Solid understanding of circuit design principles and EMIR analysis at the transistor and gate level, across multiple modes (static and dynamic) In-depth knowledge of industry-leading tools such as Redhawk, Voltus, and Totem Experience in simulation and power analysis to verify circuit performance Strong understanding of CAD flows Proficiency in scripting/programming languages (Perl and Python) Excellent communication and collaboration skills Experience developing CMOS analog and mixed-signal designs Experience applying AI/ML or LLM-based tools to EDA flow automation, anomaly detection, or signoff data analysis

Description

As a Signoff Engineer, you’ll ensure that all necessary verification and analysis work is completed on complex mixed-signal designs prior to tapeout. In this highly visible role on our advanced Signoff CAD team, you’ll work on state-of-the-art designs and apply hands-on experience in power/EMIR analysis to develop, define, and refine signoff methodologies at both the gate and transistor level. This includes, but isn’t limited to, signoff for functional static/dynamic IR analysis, scan-mode IVD analysis, package model handling, power EM analysis, signal EM, power switch modeling, and IP reuse. Our team is also evolving how we approach signoff itself — increasingly exploring AI/ML and LLM-driven techniques to accelerate analysis, automate flow debugging, and surface anomalies earlier in the design cycle. You’ll help define signoff requirements early in the project lifecycle, partner with Design, CAD, and Technology teams to confirm EDA flows and tools are set up and running correctly, and ensure all signoff criteria are met by project close. You’ll also interface directly with design groups, providing frontline support for enablement, enhancement, and debug requests.