Cadence Design Systems

Develops EDA software, IP, verification tools

Design Engineering Architect

Board & Electronics DesignConfirmed live in the last 24 hours

Full-timeBengaluru, Karnataka, IndiaNo salary listedIn-person

About the Job

Requirements

Master of Science or Ph.D. in Electrical Engineering or a similar degree.
15+ years of experience, preferably working with high-speed SerDes and PHYs.
Good understanding of high-speed SerDes architecture.
Hands-on lab experience with instruments such as high-speed oscilloscopes, TDRs, VNAs, and spectrum analyzers.
Fluency with 3D and 2.5D extraction tools such as Sigrity Clarity/PowerSI or Ansys HFSS/SIwave.
Experience with IBIS-AMI model simulations.
Experience correlating simulation results with lab measurements.
Good understanding of PCB and FCBGA design rules and requirements.
Strong debugging and problem-solving skills.
Excellent communication and presentation skills to communicate effectively with customers and internal stakeholders.

Responsibilities

Work on test chip package design SI/PI optimization and verification.
Work on evaluation board design optimization for best SI/PI performance.
Provide extracted and measured channel models for chip designers in the R&D team.
Help with package and PCB SI/PI design guidelines and customer support on SI/PI-related inquiries.
Review customer package and board designs and simulation results; help provide feedback to customers to ensure the best possible performance of the company's IP in their ASIC.
Work on link performance simulations using S-parameter channel models and IBIS-AMI behavioral models.
Help with SI/PI-related debugging of test chips or customer ASICs in the lab.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

JOb Profile

This is a unique opportunity to join the HPP IP R&D Group at Cadence Design Systems. We are looking for a Sr Principal SI/PI Engineer who will be a key contributor to our advanced high speed IP products. This is a hands-on technical position.

Main Job Tasks and Responsibilities:

Work on test chip package design SI/PI optimization and verification.
Work on evaluation board design optimization for best SI/PI performance.
Provide extracted and measured channel models for chip designers in the R&D team.
Help with package and PCB SI/PI design guidelines and customer support on SI/PI related inquiries.
Review customer package and board designs and simulation results. Help with providing feedback to customers to ensure best possible performance of our IP in their ASIC.
Work on link performance simulations using S-parameter channel models and IBIS-AMI behavioral models.
Help with SI/PI related debug of test chips or customer ASICs in the lab.

Position Requirements:

M.S. or Ph.D. Electrical Engineering (or similar degree)
15+ years of experience preferably working with high speed SerDes and PHYs
Good understanding of high speed SerDes architecture
Hands on lab experience with instruments like high speed oscilloscopes, TDRs, VNAs, spectrum analyzers, etc.
Fluent with using 3D and 2.5D extraction tools like Sigrity Clarity/PowerSI or Ansys HFSS/SIwave
Experience with IBIS-AMI model simulations
Experience with simulation result to lab measurement correlation
Good understanding of PCB and FCBGA design rules and requirements
Strong debugging and problem-solving skills
Excellent communication and presentation skills to effectively communicate with both customers and internal stake holders

We’re doing work that matters. Help us solve what others can’t.

About the Company

Cadence Design Systems

Develops EDA software, IP, verification tools

Cadence Design Systems supplies software, hardware, and IP for electronic design automation (EDA) to help customers create advanced semiconductor chips and electronic systems. Its tools handle system design, verification, digital and analog IC design, and custom flows, while IP such as Tensilica processors and DSP cores can be licensed for integration into customer products. The offerings are delivered as software licenses with maintenance and support, plus IP licensing and occasional hardware-accelerated options. The company differentiates itself with a broad, end-to-end EDA portfolio and close collaboration with industry leaders to streamline the path from concept to silicon, aiming to help customers bring sophisticated silicon and electronics to market faster with lower risk and higher productivity.

Company size: 10,001+
Company stage: IPO
Headquarters: San Jose, CA
Founded: 1988

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