Tesla

Makes electric cars, robotaxis and grid batteries

DFT Intern

Hardware Validation & TestingConfirmed live in the last 24 hours

InternshipBengaluru, Karnataka, IndiaNo salary listedIn-person

About the Job

Requirements

Strong understanding of design-for-test (DFT) methodologies, including compressed scan, memory built-in self-test (MBIST), loopback, and boundary scan across digital logic, embedded memory, and input/output and physical-layer domains.
Knowledge of JTAG, IEEE 1500, and IEEE 1687.
Expertise in automatic test pattern generation (ATPG), coverage analysis, and zero-delay and SDF-based simulations.
Experience with industry-standard DFT tools such as Cadence Modus/Genus or Siemens Tessent.
Foundation in Verilog, digital logic design, circuit fundamentals, and timing analysis.
Proficiency in scripting with TCL, Python, or Perl.
Bachelor’s or Master’s degree in Electrical or Computer Engineering, or equivalent experience.

Responsibilities

Define and implement DFT features at RTL and gate levels using in-house flows.
Partner with physical design teams to achieve timing and design closure with DFT constraints.
Execute block-level scan insertion, ATPG, coverage analysis, and simulations.
Perform full-chip pattern retargeting, validation, and sign-off.
Drive design improvements to enhance test coverage and diagnosability.
Collaborate with test and product engineering on pattern delivery, silicon bring-up, debug, and characterization.

Desired Qualifications

Familiarity with BSDL, ICL, and PDL.
Experience with MBIST implementation, repair algorithms, and memory test strategies.
Exposure to SerDes and mixed-signal DFT techniques, such as IOBIST and loopbacks.
Post-silicon experience, including pattern conversion, bring-up, debug, and characterization.

Category	Tesla SI
Location	Bengaluru Urban, KA
Requisition ID	279111
Type	Intern/Apprentice

Job Description

About the Role:Tesla’s Silicon Development Group is seeking a DFT Intern to drive Design-for-Test across the design-to-production lifecycle for custom ASICs. In this role, you will own testability from design through silicon bring-up and high-volume manufacturing. You will advance state-of-the-art methodologies in test, debug, and safety to achieve high coverage, exceptional quality, and ultra-low DPPM—while optimizing test cost at scale.

Job Responsibilities

Responsibilities:

Define and implement DFT features at RTL and gate levels using in-house flows
Partner with physical design teams to achieve timing and design closure with DFT constraints
Execute block-level scan insertion, ATPG, coverage analysis, and simulations
Perform full-chip pattern retargeting, validation, and sign-off
Drive design improvements to enhance test coverage and diagnosability
Collaborate with test and product engineering on pattern delivery, silicon bring-up, debug, and characterization

Job Requirements

Requirements:

Strong understanding of DFT methodologies including compressed scan, MBIST, loopback, and boundary scan across digital logic, embedded memory, and IO/PHY domains
Solid knowledge of JTAG, IEEE 1500, and IEEE 1687; familiarity with BSDL, ICL, and PDL is a plus
Proven expertise in ATPG, coverage analysis, and both zero-delay and SDF-based simulations
Experience with industry-standard DFT tools such as Cadence Modus/Genus or Siemens Tessent
Strong foundation in Verilog, digital logic design, circuit fundamentals, and timing analysis
Proficiency in scripting (TCL, Python, or Perl)
Experience with MBIST implementation, repair algorithms, and memory test strategies is a plus
Exposure to SerDes and mixed-signal DFT techniques (e.g., IOBIST, loopbacks) is a plus
Post-silicon experience including pattern conversion, bring-up, debug, and characterization is a plus
Bachelor’s or Master’s degree in Electrical or Computer Engineering (or equivalent experience)

Tesla

DFT Intern

About the Job

Requirements

Responsibilities

Desired Qualifications

Job Description

Job Responsibilities

Job Requirements

About the Company

Tesla

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