Experienced Analog IC Designer

onsemi is seeking an experienced Analog IC Designer to join its Core Analog IP Development Centre of Excellence in Cork, Ireland. You will develop power, clock, monitoring and reset IP for the Treo platform in BCD65 technology, combining hands-on circuit design with substantial architecture involvement and cross-product-line technical engagement.

This role extends well beyond individual block delivery. You will help shape platform-level analog IP architectures, translate product-line requirements into actionable IP roadmaps for the Core Analog teams, and champion IP reuse across the platform. You will also mentor junior engineers and guide designs from concept and specification through silicon validation and mass production.

• A bachelor’s degree in electrical or electronic engineering, or a closely related discipline, with at least 15 years of relevant analog IC design experience; or a master’s degree in a relevant discipline with at least 11 years of relevant analog IC design experience.
• Demonstrated hands-on design experience with bandgap references, LDOs, DC–DC regulators, oscillators and PLLs.
• A proven track record of taking several products through the full development lifecycle to mass production, including silicon evaluation, debugging and production support.
• Strong analog circuit fundamentals and practical expertise in transistor-level design, simulation, layout-dependent effects and post-layout verification.
• Substantial architecture experience, with the ability to assess system-level requirements and translate them into robust, reusable analog IP solutions.
• Experience engaging with product lines and translating competing product requirements into coherent IP specifications, development priorities and roadmaps.
• Demonstrated experience mentoring junior engineers and providing technical leadership through design and architecture reviews.
• Strong communication and presentation skills, with the ability to explain complex technical concepts, present trade-offs and build alignment across engineering teams and product stakeholders.
• A solid understanding of how AI can contribute to analog design and layout, including practical use cases, limitations and the need for independent engineering verification.

Desirable Experience

• Experience in BCD technologies, particularly BCD65, and analog IP development for mixed-signal platforms.
• Experience with supply and voltage monitoring, power-on reset, brownout detection and power or clock sequencing.
• Experience defining reusable IP portfolios, configuration strategies and integration requirements across multiple product families.
• Practical experience with scripting, design-flow automation or evaluation of AI-assisted engineering tools.

Architecture, Product Engagement and IP Roadmaps

• Play a leading technical role in defining architectures for power, clock, monitoring and reset IP in the Treo BCD65 platform.
• Engage directly with product-line architects, design teams and stakeholders to understand product needs, operating conditions, integration constraints and future requirements.
• Translate these needs into clear IP specifications and prioritised development roadmaps for the Core Analog teams, balancing immediate product commitments with longer-term platform requirements.
• Drive architecture trade-offs across performance, power, area, robustness, testability and integration complexity.
• Champion reusable IP architectures, configurable features and consistent interfaces that support adoption across multiple products while limiting unnecessary customisation.
• Communicate architecture proposals, roadmap priorities and technical decisions clearly through design reviews, presentations and written documentation.

Analog Design and Production Delivery

• Design and develop analog IP including bandgap references, low-dropout regulators (LDOs), DC–DC regulators, oscillators, phase-locked loops (PLLs), monitoring circuits and reset functions.
• Own block development from specification and circuit architecture through transistor-level design, simulation, layout guidance, verification and silicon characterisation.
• Verify performance across process, voltage and temperature corners, including mismatch, noise, stability, start-up behaviour and relevant operating modes.
• Work closely with layout engineers to address matching, parasitics, isolation, coupling and device reliability, and ensure post-layout performance meets specifications.
• Collaborate with product integration, validation, test and product engineering teams to resolve issues and support successful transfer to mass production.
• Create clear design documentation, integration guidance and characterisation reports that enable efficient IP reuse and maintenance.

Technical Leadership, Mentoring and AI Adoption

• Mentor junior engineers in analog design fundamentals, architecture evaluation, simulation methodology, design reviews and silicon debug.
• Provide technical guidance and constructive design feedback, sharing knowledge and strengthening engineering practices across the Core Analog teams.
• Help identify and assess practical opportunities for AI-assisted analog design and layout, including design-space exploration, simulation automation, results analysis, documentation and layout assistance.
• Apply sound engineering judgement when evaluating AI-generated outputs, retaining rigorous verification, traceability and protection of confidential design information.