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MaxLinear

Fabless RF/analog/mixed-signal IC designer

Principal Engineer Memory Architect

Silicon & ASIC DesignPosted on Nov 5
Full-timeCarlsbad, CA, USAIn-person

About the Job

Requirements

  • Deep understanding of embedded SRAM and register-file architectures, including bit-cell fundamentals, array layout considerations, and PPA trade-offs.
  • Strong knowledge of low-power techniques, read/write assist techniques, design stability and robustness, design margining, and power integrity considerations.
  • Experience analyzing memory behavior across PVT corners and evaluating timing, reliability, signal integrity, and SoC-level trade-offs.
  • Strong understanding of memory compiler flows and verification methodologies, with the ability to assess compiled and custom memory solutions.
  • Excellent communication skills and ability to collaborate effectively across multidisciplinary teams and influence technical decisions at strategic and hands-on levels.
  • Bachelor of Science in Electrical Engineering with 9 years of experience, or a master's degree with 7 years of experience, or a Ph.D. with 4 years of experience.

Responsibilities

  • Design, define, evaluate, and optimize memory intellectual property across advanced technology nodes.
  • Leverage memory architecture expertise, circuit-level understanding, and system-level awareness to deliver high-performance, power-efficient, area-optimized, and reliable memory solutions for SoC integration.
  • Work closely with IP and SoC teams to provide technical direction for memory IP roadmaps, architecture selection, compiler evaluation, and PPA and robustness trade-off decisions.
  • Own the design and optimization of memory architectures based on SRAMs, ROMs, and register files, using memory compilers or custom designs.
  • Deliver competitive memory IP solutions and enable seamless integration into SoCs.
  • Collaborate with cross-functional engineering teams and external IP vendors, and develop scalable QA methodologies, automation flows, and verification frameworks for consistent memory IP evaluation.

Desired Qualifications

  • Proficiency with EDA and analysis tools HSPICE, Spectre, and Python, and related memory verification or modeling environments.
  • Familiarity with SoC design flows and interactions among memory IP, standard cells, I/O libraries, clocking, system buses, and interface protocols.
  • Familiarity with ROMs, flash memories, and OTPs.
  • Understanding of advanced-node scaling, PVT variation impacts, memory behavior across corners, and silicon validation practices.
  • Familiarity with transistor-level circuit design and analysis, and experience using IC design or simulation tools such as HSPICE, Spectre, or Cadence Virtuoso.
  • Experience with QA methodologies, validation frameworks, and technical roadmaps.

About the Company

MaxLinear

Fabless RF/analog/mixed-signal IC designer

MaxLinear designs and sells RF, analog, and mixed-signal ICs for broadband, connectivity, infrastructure, and industrial markets. It offers system-on-chip solutions for cable broadband, fiber-to-the-home networks, and Wi-Fi, plus RF transceivers and high-speed interconnects for data centers, set-top boxes, automotive video systems, and mobile devices. It is a fabless company that outsources manufacturing to foundries like UMC and targets OEM, ODM, and module makers, expanding its portfolio through acquisitions such as Exar, Intel’s Home Gateway Platform Division, and NanoSemi. Its goal is to provide scalable, high-quality semiconductor solutions that enable reliable connectivity across home, mobile, automotive, and data-center applications, while growing through diversified products and strategic acquisitions.

Company size
1,001-5,000
Company stage
IPO
Headquarters
Carlsbad, CA
Founded
2003

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