Emulation Verification Engineer - Japan Design Center

Summary

Imagine what you could do at Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, smart people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Are you passionate about changing the world? We have a critical impact on getting high quality functional products to millions of customers quickly. We are looking for you to join our emulation team focusing on the creation, deployment, and support of advanced emulation environments. In this highly visible role, you will be at the center of a chip design effort collaborating with all disciplines. Are you ready to help us deliver the next groundbreaking Apple products?

Minimum Qualifications

Bachelor degree with relevant major and, ideally, relevant industry experience Experience with SystemVerilog, Verilog or UVM Experience in creating test benches from scratch (Block and System Level) Experience in Regression Management and Triaging

Preferred Qualifications

Experience with bring up, debugging and verification in Emulation Understanding of the tool flow from RTL to Emulation Good understanding of any Standard Emulator (Palladium, Veloce, Zebu) OR FPGA (Xilinx, Altera) flow Proven Design Verification or Silicon Validation skills Experience in writing Synthesizable SystemVerilog/Verilog code and SystemVerilog assertions Experience with SystemVerilog verification environments including C/C++ DPI, UVM Experience with any Scripting (Perl/Python/TCL) Excellent analytical and debug skills Hands on usage of Low Power methodologies (UPF based preferably) Experience in UVM Acceleration

Description

As a member of the Emulation Verification team, you will play a key role in utilizing Emulation for verification of large Display and Wireless SoCs. You will also be involved in the most cutting-edge technology of bringing in mixed signal models onto the Palladium platform. The overall work will involve porting the design onto the Palladium platform, followed by executing the detailed emulation test plan.

Responsibilities

Working closely with emulation team to bring up large Display and Wireless SoCs along with their mixed signal components on the emulation platform Developing/utilizing monitors and checkers on the emulation platform Preparing and executing the test plan and performing reviews with the cross functional teams Collaborating cross functionally with Design, Architecture, Power, Silicon Validation, Performance and SW Teams Developing code for Design and verification that aids with emulation activities, using Verilog/SystemVerilog/UVM