ASIC RTL Design Engineer - SI Math & Computer Hardware

Job Description

The Tesla SI Hardware team is at the forefront of revolutionizing artificial intelligence through cutting-edge hardware innovation. Comprising brilliant engineers and visionaries, the team designs and develops advanced SI inference chips tailored to accelerate Tesla’s machine learning capabilities. A key part of this effort is Dojo, Tesla's custom supercomputer system built to efficiently train massive neural networks on vast video data from the fleet. The work of Tesla's SI Hardware team powers the neural networks behind Full Self-Driving (FSD), and Tesla humanoid robot, Optimus, pushing the boundaries of computational efficiency and performance. By creating custom silicon and optimized architectures, the team ensures Tesla remains a leader in AI-driven automotive and energy solutions, shaping a future where intelligent machines enhance human life.

Tesla's SI hardware team is seeking a highly motivated ASIC RTL Design Engineer with a specialization in the mathematical and computational aspects of custom SI accelerators. You will focus on designing high-performance, power-efficient RTL for math-intensive components that power our SI training and inference systems. This role emphasizes expertise in tensor operations, matrix computations, and optimized data paths for advanced SI workloads.  This role is located in Palo Alto, CA or Austin, TX.  If you are passionate about pushing the boundaries of low-precision arithmetic, quantization techniques, and hardware acceleration for machine learning, this is your opportunity to contribute to revolutionary SI hardware.

Job Responsibilities

• Micro-architect and implement RTL for specialized math units, including tensor cores, matrix multiplication engines, and SIMD (Single Instruction, Multiple Data) data paths
• Optimize designs for low-precision math operations (e.g., FP8, INT4/8) to maximize throughput while maintaining accuracy for SI models
• Develop and integrate block quantization formats, such as those used in model compression, ensuring seamless hardware support for quantized neural networks
• Design look-up tables (LUTs) for efficient approximation of non-linear functions, activation functions, and other compute-intensive operations
• Collaborate with SI architects and software teams to define functional requirements for math-heavy pipelines, focusing on data flow, parallelism, and precision trade-offs
• Perform RTL coding in Verilog/SystemVerilog, with an emphasis on modular, reusable designs for complex arithmetic units
• Participate in design reviews, simulation, and verification to ensure correctness of math operations under various edge cases, including overflow, underflow, and quantization errors
• Analyze performance metrics (e.g., area, power, latency) for math datapaths and propose optimizations to meet aggressive SI hardware targets
• Work closely with physical design and verification teams to bring designs from concept to silicon, with a focus on high-speed, high-density compute blocks

Job Requirements

• Degree  in Electrical Engineering, Computer Engineering, a related field, or equivalent experience
• 3+ years of experience in ASIC RTL design, with a proven track record in math-oriented hardware components for AI/ML accelerators (e.g., GPUs, TPUs, or custom ASICs)
• Deep understanding of tensor cores and matrix multiplication architectures, including systolic arrays, GEMM optimizations, and fused multiply-add (FMA) units
• Expertise in data path design for SIMD/VLIW processors, including vector registers, ALU pipelines, and parallelism techniques
• Hands-on experience with low-precision math, including floating-point and integer formats, rounding modes, and error analysis for SI applications
• Familiarity with block quantization formats (e.g., per-tensor, per-channel quantization) and their implementation in hardware for efficient inference
• Proficiency in using look-up tables for function approximation, such as in sigmoid/tanh activations or transcendental functions
• Strong skills in Verilog/SystemVerilog, with experience in synthesis tools (e.g., Synopsys DC) and simulation environments (e.g., VCS, Verdi)
• Knowledge of SI frameworks (e.g., TensorFlow, PyTorch) and how hardware math units interact with software kernels is a plus
• Excellent problem-solving abilities, with a passion for optimizing compute efficiency in resource-constrained environments