Cadence Design Systems

Develops EDA software, IP, verification tools

Principal Design Engineer

Silicon & ASIC DesignConfirmed live in the last 24 hours

Full-timeBengaluru, Karnataka, IndiaNo salary listed

About the Job

Requirements

A Master of Science or Bachelor of Technology degree in Electrical Engineering, Computer Engineering, Electronics Engineering, or a similar discipline is required.
At least 7 years of experience is required.
Demonstrated knowledge of DDR4/5 and LPDDR4/5 intellectual property is required.
Hands-on design and verification experience with DDR protocols is required.
Experience with DDR integration and verification at the system-on-chip level is required.
Experience with silicon bring-up and testing for DDR is required.
Hands-on design and verification experience with Advanced Microcontroller Bus Architecture protocols, including AXI, AHB, and APB, is required.
Experience with Cadence tools is required.
Experience with lint, clock-domain crossing, synthesis, and static timing analysis review is required.
Exposure to major integrated-circuit implementation, design, and verification tools is required.
Willingness to travel to customer sites worldwide is required.
Ability to work with global teams across different time zones is required.

Responsibilities

Support integration, customization, and post-silicon bring-up of Cadence DDR intellectual property subsystems.
Analyze and resolve complex subsystem application or implementation issues and provide professional guidance to customers.
Support DDR controller and physical-layer system-on-chip integration reviews and answer integration questions.
Perform register-transfer-level and gate-level simulations to verify functionality.
Assist customers with gate-level simulations and timing closure.
Participate in developing documentation and checklists for customers.
Support post-silicon bring-up and deployment activities for customers.
Provide prompt updates to customers to enhance the customer experience.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Position Requirements
- M.S. or BTech Electrical/Computer/Electronics Engineering (or similar degree)
- Experience - 7+ years
- sound knowledge of DDR4/5, LPDDR4/5 IP.
- Hands on design/verification experience on DDR protocol
- Exposure to DDR Integration and Verification at SOC Level
- Exposure to Silicon Bring-up/Testing for DDR.
- Hands on design/verification experience on AMBA based protocols like AXI, AHB, APB
- Experience on cadence tools
- Exposure to Lint/CDC, Synthesis, Static Timing Analysis review
- Exposure to all major IC implementation, design, and verification tools.
- Willing to travel to customer sites worldwide.
- Working with global (US, west coast, and east coast) teams, which work in different time-zones.

Primary Responsibilities:
- Responsible for supporting integration / customization / post silicon bring up of CDNS DDR IP subsystems.
- Analyze and resolve complex subsystem application or implementation issues and provide professional guidance to customers.
- Support DDR Controller and PHY SOC integration reviews, and integration questions.
- Perform RTL and gate level simulations to verify functionality.
- Assist customers with gate level simulations and timing closure.
- Participate in development of CDNS documentations and checklists for customers.
- Support post silicon bring-up and deployment activities by our customers.
- Enhance customer experience by providing prompt updates to customers.

We’re doing work that matters. Help us solve what others can’t.

About the Company

Cadence Design Systems

Develops EDA software, IP, verification tools

Cadence Design Systems supplies software, hardware, and IP for electronic design automation (EDA) to help customers create advanced semiconductor chips and electronic systems. Its tools handle system design, verification, digital and analog IC design, and custom flows, while IP such as Tensilica processors and DSP cores can be licensed for integration into customer products. The offerings are delivered as software licenses with maintenance and support, plus IP licensing and occasional hardware-accelerated options. The company differentiates itself with a broad, end-to-end EDA portfolio and close collaboration with industry leaders to streamline the path from concept to silicon, aiming to help customers bring sophisticated silicon and electronics to market faster with lower risk and higher productivity.

Company size: 10,001+
Company stage: IPO
Headquarters: San Jose, CA
Founded: 1988

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