Cadence Design Systems

Develops EDA software, IP, verification tools

Lead Design Engineer

Hardware Validation & TestingConfirmed live in the last 24 hours

Full-timeBengaluru, Karnataka, IndiaNo salary listedIn-person

About the Job

Requirements

A BE, BTech, ME, or MTech degree in Electrical, Electronics, or VLSI is required.
Six to ten years of core RTL integration and verification experience using Verilog is required.
Experience with SystemVerilog and use or debugging of a Universal Verification Methodology-based environment is required.
Experience as a design verification engineer, with substantial recent experience in RTL integration and verification, is required.
Experience implementing complex protocols is required.
Proficiency in ASIC development flows such as lint, clock-domain crossing, synthesis, preferably using Genus, and static timing analysis is required.
Ability to debug and set up new flows is required.

Responsibilities

Integrate, verify, and release Cadence IP solutions for different customers.
Work with existing RTL and integrate the PHY and controller to create the subsystem.
Add new features to the RTL.
Ensure customer configurations are clean through verification regressions.
Support customers.
Ensure the design meets lint and clock-domain crossing design guidelines.

Desired Qualifications

Experience with PCIe, CXL, or IDE is highly desirable.
Prior experience in IP development teams is an added advantage.
Scripting knowledge is an advantage.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Position Description:

IP Integration and release Engineer for SSG IP Release engineering team.
Position is based in Bangalore.
The role would include IP integration, verification, and release of the IP solution of Cadence to different customers.
The work involved will be working with the existing RTL, integration of the PHY and controller to create the sub-system, addition of new features into the RTL, ensuring various customer configurations are clean as part of verification regressions, supporting customers, ensuring design is clean for LINT and CDC design guidelines.
Proficient in ASIC development flows like Lint/CDC/Synthesis (preferably with Genus)/STA. Ability to debug and setup new flows.

Position Requirements:

BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design verification engineer, with a large portion of the recent work experience on RTL integration and verification.

6-10 years of core RTL integration and verification experience using Verilog is a must.

System Verilog experience and experience with UVM based environment usage / debugging is required.
PCIe/CXL/IDE experience is highly desirable. Prior experience in implementation of complex protocols is a must.
Prior experience in IP development teams would be an added advantage.

Scripting knowledge is an advantage.

We’re doing work that matters. Help us solve what others can’t.

About the Company

Cadence Design Systems

Develops EDA software, IP, verification tools

Cadence Design Systems supplies software, hardware, and IP for electronic design automation (EDA) to help customers create advanced semiconductor chips and electronic systems. Its tools handle system design, verification, digital and analog IC design, and custom flows, while IP such as Tensilica processors and DSP cores can be licensed for integration into customer products. The offerings are delivered as software licenses with maintenance and support, plus IP licensing and occasional hardware-accelerated options. The company differentiates itself with a broad, end-to-end EDA portfolio and close collaboration with industry leaders to streamline the path from concept to silicon, aiming to help customers bring sophisticated silicon and electronics to market faster with lower risk and higher productivity.

Company size: 10,001+
Company stage: IPO
Headquarters: San Jose, CA
Founded: 1988

Recently Posted Jobs

Explore more opportunities at Cadence Design Systems

See more jobs