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Axiado

AI-driven hardware security solutions for infrastructure

ASIC Design Engineer

Silicon & ASIC DesignConfirmed live in the last 24 hours
Full-timeTaipei City, TaiwanNo salary listedIn-person

About the Job

Requirements

  • At least 8 years of experience in RTL logic design, verification, synthesis, and timing optimization.
  • Proficiency in writing clear, implementable micro-architecture specifications.
  • Expertise in writing efficient RTL code in Verilog and SoC integration.
  • A good understanding of assertions, coverage analysis, RTL synthesis, and timing closure.
  • Experience working with interface protocols such as PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, and UART.
  • Experience with design bring-up and debugging on FPGA-based emulation platforms such as HAPS and Veloce.
  • Fluency with scripting languages such as Perl and Python.
  • Must have completed at least one tapeout.
  • Experience with repository management tools such as Bitbucket and Jenkins, and bug-tracking tools such as JIRA.

Responsibilities

  • Help develop and implement SoCs.
  • Design micro-architecture; perform RTL coding, synthesis, timing closure, and documentation for various RTL blocks.
  • Optimize performance, bandwidth, and power at the top and block levels.
  • Work with FPGA engineers on early prototyping.
  • Support test program development, chip validation, and chip life through production maturity.
  • Collaborate with firmware, software, design verification, FPGA, design-for-test, SoC integration, and backend teams throughout ASIC development.

Desired Qualifications

  • Silicon bring-up and debugging experience.

About the Company

Axiado

AI-driven hardware security solutions for infrastructure

Axiado provides AI-driven hardware security solutions that protect digital infrastructure by embedding security into servers, 5G networks, and data centers. Its core offerings—the Secure Vault core and Secure AI preemptive threat detection engine—are built into Trusted Control Units (TCUs) and deliver real-time, proactive AI-based threat detection. The TCUs are Open Compute Project (OCP) compliant, enabling faster adoption across cloud datacenters, 5G base stations, switches, and power controllers. Unlike software-only defenses, Axiado combines hardware security modules with software to meet the needs of enterprises requiring high assurance. The goal is to make data security the default across the infrastructure chain and reduce the global economic impact of cybercrime.

Company size
51-200
Company stage
Series C
Total funding
$205M
Headquarters
San Jose, CA
Founded
2017

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