Cadence Design Systems

Develops EDA software, IP, verification tools

Customer Engagement Engineer 2

Solution EngineeringConfirmed live in the last 24 hours

Full-timeGyeonggi-do, South KoreaNo salary listedIn-person

About the Job

Requirements

A minimum bachelor's-level degree in Computer Science or Electrical Engineering and 3–5 years of industry experience are required.
At least 3 years of hands-on, high expertise in hardware design and verification techniques are required.
Hands-on experience using an HDL simulator such as IES, VCS, or Questa is required; IES is preferred.
Experience with RTL design or verification using Verilog, SystemVerilog, C/C++, or SystemC is required.
Understanding of standard bus protocols such as AMBA or interface protocols is required.
Hands-on verification experience using SystemVerilog, Verilog, VHDL, or SystemC is required.
Hands-on design experience using SystemVerilog, Verilog, and VHDL is required.
Knowledge of VIPs, code coverage, functional coverage tools, and related technologies is required.
Good communication skills in English and a strong desire to work in a global environment with customers and business unit colleagues are required.

Responsibilities

Work with R&D to identify and scope opportunities for the Cadence functional logic verification platform.
Understand goals and objectives, then plan, execute, and manage key technical evaluations by proactively collaborating with existing and potential customers and team colleagues.
Summarize tasks and projects, report to the manager, and communicate effectively with the team.
Train, ramp up, and accompany customer projects.
Conduct basic and advanced training, presentations, and demonstrations as needed.
Ramp up other team members on advanced verification technologies and tools.
Provide technical expertise to address client queries requiring expert involvement.

Desired Qualifications

Experience with the UVM methodology or a similar methodology is preferred.
Knowledge of Metric Driven Verification (MDV) using vManager CS is preferred.
Hands-on experience optimizing RTL and gate-level simulation performance using standard profiling tools is a plus.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Work with R&D to identify and scope opportunities for the Cadence functional logic verification platform
Understand the Goal and Objective, then plan and execute and manage key technical evaluations by co-working proactively with existing and potential customers as well as team colleagues
Summarize the tasks and projects, and report to manager and share with team effectively
Train, ramp-up and accompany customer project.
Conduct basic and advanced trainings, presentations and demos as necessary.
Ramp-up other members of the team on the advanced verification technologies and tools.
Providing technical expertise to address clients’ queries, which need expert involvement

The candidate should possess minimum BS level of CS or EE with 3-5 years of industry experience.
Minimum 3 years hands-on, high expertise on hardware design & verification techniques.
Hands on experience using HDL simulator (e.g. ies, vcs or questa, but ies preferred) is a must.
Experience of RTL design or verification with Verilog / SV Language or C/C++ or System C.
Understanding standard BUS protocol like AMBA or interface protocol.
Hands on Verification experience using SystemVerilog/Verilog/VHDL/SystemC.
Experience on UVM methodology or similar one should be preferred.
Hands on Design experience using SystemVerilog, Verilog and VHDL.
Knowledge of VIPs, and code & functional coverage tools (IMC preferred) and technologies.
Knowledge of Metric Driven Verification (MDV) using vManager CS should be preferred.
Hands-on experience optimizing RTL, Gate-level simulation for improving performance by using standard profiling tools is a big plus.
Good communication skills in English and a strong desire for working in a global environment with customers and BU people.

We’re doing work that matters. Help us solve what others can’t.

About the Company

Cadence Design Systems

Develops EDA software, IP, verification tools

Cadence Design Systems supplies software, hardware, and IP for electronic design automation (EDA) to help customers create advanced semiconductor chips and electronic systems. Its tools handle system design, verification, digital and analog IC design, and custom flows, while IP such as Tensilica processors and DSP cores can be licensed for integration into customer products. The offerings are delivered as software licenses with maintenance and support, plus IP licensing and occasional hardware-accelerated options. The company differentiates itself with a broad, end-to-end EDA portfolio and close collaboration with industry leaders to streamline the path from concept to silicon, aiming to help customers bring sophisticated silicon and electronics to market faster with lower risk and higher productivity.

Company size: 10,001+
Company stage: IPO
Headquarters: San Jose, CA
Founded: 1988

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