CPU Implementation Lead Engineer

Summary

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver groundbreaking Apple products! Apple’s Silicon Engineering Group (SEG) is hiring experienced engineers for the CPU Implementation leadership team.

Minimum Qualifications

Minimum BS and 10+ years of relevant industry experience Experience in driving chip implementation from definition phase to silicon correlation Experience working with cross-functional teams spanning technology, architecture, RTL & Physical design Experience in synthesis & place-and-route

Preferred Qualifications

Familiarity with high performance microprocessor architecture fundamentals Experience in leading initiatives for improving power, performance, & area on CPUs Knowledge of logic design principles along with timing and power implications Understanding of low power microarchitecture and implementation techniques Experience with scripting in Perl and/or TCL Design experience in deep submicron technologies and basic transistor level design and device physics

Description

As a CPU Implementation Lead Engineer, you will own or participate in the following: • CPU IP delivery • Work with multi-functional engineering teams to implement and validate physical design in the aspects of timing, power, area, electrical analysis, functionality, reliability, and testability • Work extensively with the partition implementation team to make area/frequency/performance/power tradeoffs and remove bottlenecks in meeting design targets and delivery schedule • Participate in the definition and enhancement of RTL-to-GDS flow through synthesis and place-and-route targeting aggressive targets for power, performance, and area • Mentor junior engineers