Cadence Design Systems

Develops EDA software, IP, verification tools

Lead Design Engineer

Embedded EngineeringConfirmed live in the last 24 hours

Full-timeBengaluru, Karnataka, IndiaNo salary listedIn-person

About the Job

Requirements

4-6 years of experience developing bare-metal firmware for high-speed SerDes or memory interface physical-layer blocks.
Knowledge of the C programming language for embedded software development and experience using a relevant integrated development environment.
Ability to debug register-transfer-level simulations involving firmware and a microcontroller subsystem.
Knowledge of Shell, Perl, Python, and Tcl scripting.
Experience using verification electronic design automation tools such as simulators and waveform viewers.
Ability to debug firmware and hardware issues.
Good communication skills.

Responsibilities

Develop firmware for DDR, LPDDR, GDDR, and HBM physical-layer blocks using microcontrollers.
Develop firmware in C and similar embedded programming languages, including bare-metal programming and low-level application programming interfaces on microcontrollers.
Collaborate with hardware designers and memory subsystem architects to derive algorithms and implement them.
Collaborate with the verification team to develop a firmware-hardware co-verification plan.
Debug firmware-based simulations in hardware behavioral simulations, including register-transfer-level simulations with firmware for verification.
Debug issues on emulation and silicon bring-up boards.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Be part of the Cadence Memory IP Group adn responsible for -

Developing firmware for DDR/LPDDR/GDDR/HBM PHY using microcontrollers
Responsible for developing firmware in C and similar Embedded programming languages typically involving bare-metal programming and developing low level APIs on Microcontrollers.
Responsible for collaborating with hardware designers and memory subsystem architects to derive algorithms and implement them.
Responsible for collaborating with verification team to deduce firmware-hardware co-verification plan.
Support debug of firmware-based simulations in hardware behavioral simulations (RTL simulations with firmware for verification)
Support debugging issues on emulation and Silicon bring-up boards.

Required Skills:

4-6 years of experience in developing bare-metal firmware for High-speed Serdes or Memory interface Physical Layer blocks.
Good Knowledge C programming language for embedded software development and use of relevant IDE.
Comfortable debugging RTL simulations involving firmware and microcontroller subsystem.
Good knowledge of Shell/Perl/Python/TCL scripting
Good debugging skills
Good experience on Verification EDA Tools like simulators and waveform viewers
Good communication Skill

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About the Company

Cadence Design Systems

Develops EDA software, IP, verification tools

Cadence Design Systems supplies software, hardware, and IP for electronic design automation (EDA) to help customers create advanced semiconductor chips and electronic systems. Its tools handle system design, verification, digital and analog IC design, and custom flows, while IP such as Tensilica processors and DSP cores can be licensed for integration into customer products. The offerings are delivered as software licenses with maintenance and support, plus IP licensing and occasional hardware-accelerated options. The company differentiates itself with a broad, end-to-end EDA portfolio and close collaboration with industry leaders to streamline the path from concept to silicon, aiming to help customers bring sophisticated silicon and electronics to market faster with lower risk and higher productivity.

Company size: 10,001+
Company stage: IPO
Headquarters: San Jose, CA
Founded: 1988

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