CPU Post-Silicon Validation Engineer – Lead/Staff/Sr Staff - Hardware Engineering

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

As a CPU Validation Engineer, you will be responsible for validating next-generation CPU designs on Emulation and Post Silicon platforms. You will work closely with design, verification, and software teams to ensure the CPU meets , functionality, and performance . You will also be responsible to debug and Root cause CPU issues reported by different teams

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Key Responsibilities:

• Develop and execute validation plans for CPU features and architecture.
• Perform post-silicon validation and bring-up of CPU cores.
• Run validation test content to qualify feature functionality and identify bugs.
• Analyze execution data and performance metrics to optimize validation efficiency.
• Debug and isolate system/platform issues using hardware and software tools.
• Collaborate with cross-functional teams to reproduce and resolve silicon failures.
• Suggest and architect new features for future CPU designs.

Required Qualifications :

• Bachelor’s/Master’s/PhD in Computer Engineering, Electronics/ Electrical Engineering, or related field.
• 5-14 years of experience in CPU/system validation or silicon bring-up.
• Strong understanding of CPU architecture , CPU Power Management and microarchitecture.
• Proficiency in C/C++, Assembly.
• Experience with embedded systems, hardware debug tools, and platform-level debugging.

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