Digital SerDes Design Lead

Key Responsibilities:

• Lead the micro-architecture definition and RTL implementation of high-speed SerDes digital blocks targeting 224G PAM4 and 448G signaling, including DSP-based equalization (FFE, DFE, CTLE digital controls), CDR loop logic, and adaptation engines
• Design and optimize PHY-level digital logic including TX driver control, RX datapath, PCS sublayers, lane alignment, deskew, and gear-boxing/rate-matching logic
• Architect and implement forward error correction (FEC) encoder/decoder blocks including RS-FEC (KP4/KP8), interleaving, and low-latency FEC architectures optimized for 224G/448G link budgets
• Drive RTL design quality through lint, CDC/RDC analysis, synthesis optimization, and close collaboration with physical design and timing closure teams on advanced FinFET/GAA process nodes
• Collaborate closely with analog/mixed-signal designers on SerDes AFE integration, digital-to-analog interface specification, calibration sequencing, and AMS co-simulation bring-up
• Own design deliverables and milestones from RTL development through tapeout signoff; coordinate with verification, DFT, and backend teams to meet aggressive schedules
• Define and implement auto-negotiation, link training, and PHY initialization state machines compliant with IEEE 802.3
• Develop power-efficient digital architectures with emphasis on clock gating, voltage scaling, and low-power design techniques for data center and AI/ML interconnect applications
• Participate in standards bodies and stay current with emerging 224G/448G specifications, OIF CEI, and next-generation interconnect standards
• Design firmware-accessible register interfaces, configuration/calibration logic, and DPI-based firmware co-simulation hooks for PHY bring-up and debug
• Support post-silicon characterization and debug activities; correlate silicon measurements with pre-silicon simulation results to drive design improvements

Qualifications:

• Masters or Ph.D in Electrical Engineering, Computer Engineering, or related fields
• 12+ years of experience in digital design of high-speed SerDes, PHY, or transceiver IPs with proven tapeout experience at 112G PAM4 or higher data rates
• Strong RTL design skills in SystemVerilog with deep understanding of synthesis, timing closure, CDC/RDC, and design-for-test (DFT) methodologies
• Expert-level knowledge of SerDes DSP architectures including FFE, DFE, MLSE, CTLE digital controls, CDR loop dynamics, and adaptation/calibration algorithms for PAM4 signaling
• Strong working knowledge of IEEE 802.3 (100G/200G/400G/800G/1.6T), OIF CEI specifications, FEC architectures (RS-FEC KP4/KP8), and/or die-to-die standards such as UCIe
• Hands-on experience with high-speed digital design on advanced process nodes (5nm, 3nm, or below) with understanding of FinFET/GAA device implications on circuit performance and power
• Experience working at the digital-analog boundary including specification of DAC/ADC interfaces, calibration state machines, and integration with mixed-signal simulation environments
• Demonstrated technical leadership with ability to mentor engineers, drive architectural decisions, and deliver silicon on aggressive schedules in startup or high-growth environments
• Experience with optical/electrical interconnects (VCSEL, EML), chiplet D2D interfaces, DRAM PHYs, or HBM memory interfaces a plus