Q

Qualcomm

Designs mobile chips and licenses wireless patents

RTL Synthesis Methodology Principal/ Sr Staff Engineer - Hardware Engineering

Silicon & ASIC DesignUpdated on Nov 11
Full-timeBengaluru, Karnataka, IndiaNo salary listedIn-person

About the Job

Requirements

  • A Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field and 8 or more years of Hardware Engineering or related work experience; OR a Master's degree in those fields and 7 or more years of experience; OR a PhD in those fields and 6 or more years of experience.
  • At least 15 years of experience in ASIC CAD flow development, Physical Design, or Synthesis Methodology.
  • A Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
  • Deep expertise with Synopsys Fusion Compiler or Design Compiler and Cadence Genus, with a track record of solving complex PPA challenges.
  • Hands-on expertise with Logic Equivalence Checking tools, including Cadence Conformal LEC and Synopsys Formality, and debugging difficult non-equivalent points in datapath-heavy designs.
  • Strong understanding of Static Timing Analysis, SDC constraint generation and validation, and tools including PrimeTime and GCA/Fishtail.
  • Advanced proficiency in Tcl and Python for flow development and data analysis.

Responsibilities

  • Lead definition, development, and deployment of the global RTL Synthesis Reference Flow using Fusion Compiler and Genus across multiple technology nodes.
  • Drive RTL-to-GDS co-optimization initiatives and collaborate with RTL and Physical Design teams to achieve measurable PPA improvements through advanced synthesis techniques.
  • Architect and maintain the Low Power (UPF/IEEE 1801) implementation methodology, drive the Static Low Power checking flow (CLP/VCLP), and verify power intent from RTL to netlist.
  • Own Logic Equivalence Checking flows for complex datapaths, retiming, and functional ECOs; manage constraints and improve early Static Timing Analysis signoff quality.
  • Serve as the primary technical interface with Synopsys and Cadence; drive tool roadmaps, manage beta evaluations, and file enhancements to address gaps between foundry claims and actual product PPA.
  • Oversee development of scalable automation in Python and Tcl to integrate synthesis with DFT insertion and netlist signoff.
  • Mentor CAD engineers by providing technical guidance on complex debugging, flow architecture, and best practices.

Desired Qualifications

  • Knowledge of UPF/CPF flows, multi-voltage domains, power gating, and retention.
  • Experience with Physical Synthesis technologies, including DEF-based flow, iSpatial, and physical guidance, and correlation with place-and-route tools such as Innovus and ICC2.
  • Familiarity with RTL-integrated DFT flows, including scan stitching and MBIST insertion, and their impact on timing and congestion.
  • Ability to lead cross-site projects, influence design methodologies, and manage stakeholder expectations.
  • Experience with AI/ML-driven CAD tools such as Fusion.ai and Cerebrus for design space exploration.

About the Company

cb

Qualcomm

Designs mobile chips and licenses wireless patents

Qualcomm designs the Snapdragon processors and modems inside many Android phones, and it licenses its wireless patents to device makers around the world. It helped commercialize CDMA, the cellular technology behind 3G networks, and its patents cover core parts of the 4G and 5G standards that phones use to connect. The company does not run its own chip factories; contract foundries make its chips, which it sells to makers of phones, PCs, cars, and connected devices. Device makers also pay Qualcomm royalties for using its patented technology, which forms a second business alongside chip sales. Qualcomm was founded in 1985 and is based in San Diego, California.

Company size
10,001+
Company stage
IPO
Headquarters
San Diego, CA
Founded
1985

Recently Posted Jobs

Explore more opportunities at Qualcomm

See more jobs