DFT Engineer - Hardware Engineering

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

As a DFT engineer, you will be working on end-to-end Custom Silicon Design cycle, from DFT-architecture planning to delivering qualified Si parts to our customers. You will be using some the best industry-standard tools and specific workflows to implement full chip level advanced Scan and MBIST insertion, verification, and pattern generation. Your role will involve collaborating closely with customers, working hand-in-hand with RTL/PD teams and supporting Test/Product Engineering teams.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

What you'll do: 

• Develop and implement comprehensive DFT architectures, collaborating on early planning stages.

• Implement scan and MBIST using industry-standard EDA tools.

• Develop and execute DFT verification plans (pattern generation, fault simulation).

• Collaborate with cross-functional teams to resolve DFT-related issues.

• Document DFT architecture and verification results.

• Serve as the primary point of contact for DFT-related inquiries and lead the implementation efforts, ensuring alignment with customer requirements.

What you'll need:  

• BTech/MTech in EE or related field, 3-12 years DFT experience.

• Proven leadership in complete DFT implementation and team guidance.

• Deep understanding of advanced DFT techniques.

Nice to have  

• Experience driving DFT implementation on large designs.

• Familiarity with advanced DFT techniques (e.g. In-system test, SSN, multi-die testing).

• Silicon debug experience related to DFT.

• Tool and methodology development related to DFT.

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