GPU Physical Design Engineer - STA/Timing

Summary

Do you love creating elegant solutions to sophisticated challenges? As part of our Silicon Engineering group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processors! You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. In this job, you will be responsible for timing closure of highly complex GPU designs that go in every Apple product and will have amazing opportunities to set new standards for the next generation GPU designs. You will gain exposure to different aspects of product development, from concept to post silicon validation! You will collaborate with a variety of fields including Architecture, RTL, Synthesis, Clocking, DFT, Physical design and Post silicon engineering to ensure the best design practices are followed for a smooth timing convergence.

Minimum Qualifications

Bachelors degree in Computer Science or Computer Engineering required. Experience or coursework in one or more of the following areas: physical design, synthesis, DFT or clocking. Experience or coursework with digital logic design, RTL, DV (testing), CMOS transistor logics or VLSI concepts. Experience with scripting languages such as TCL, Python, Perl, shell scripting, etc.

Preferred Qualifications

Masters degree preferred. An internship or prior work experience in timing closure or physical design. Experience working with EDA tools and exposure to their APIs. Exposure to advanced concepts like XALK, POCVM, ETMs etc. Experience in analysis of large volume data, identifying and driving timing fixes, generate ECOs etc.

Description

In this role you will: - Interact with RTL, architecture teams to understand physical design constraints related to timing and be the central point of contact to provide these to backend design flows. - Partner with Synthesis and Physical Design teams to implement the best design optimized for power, performance and timing. - Setting up all DFT modes and making sure all test features are properly timed. - Assemble the top level design for STA ensuring accurate analysis by reviewing all the logs and reports. - Create and maintain scripts and automation to ensure high quality STA reports and work with other teams for timing closure. - Run ECO flows on the design and responsible for close timing. - Support tapeout activities by running a full suite of signoff checks to ensure a high quality silicon for manufacture. - Work with CAD and Vendors to constantly improve the flow and bring in groundbreaking features to the analysis flows.