Data Converters Mixed Signal Lead Senior Staff - ASICS Engineering

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

Senior Staff – MSIP Design (RFA Connectivity IP) – Bangalore

About the Team
Qualcomm’s RFA Connectivity team is a global organization responsible for delivering high-performance, power-efficient, and cost-optimized Connectivity IP solutions—including PMU, Transceivers, and MSIP—for Mobile, Compute, AR/VR, Automotive, and IoT products.

Our portfolio spans key connectivity technologies such asWi-Fi, Bluetooth, GNSS, and UWB, driving innovation across a wide range of devices and use cases.

Role Overview

We are seeking aSenior Engineer (10+ years of experience)to join theMSIP Bangalore Design Team. This team works closely with RF Transceiver teams to develop cutting-edge IPs for Cellular and Connectivity systems, as well as high-performance RF front-end components across advanced process nodes.

Key Responsibilities

• Lead and contribute toMSIP circuit design, with strong ownership from system definition and specification through silicon validation and debug
• Overseelayout, verification, and documentationof MSIP blocks supporting radio transceivers and SoCs
• Drive design excellence across the full lifecycle:
  • System architecture and design trade-offs
  • Circuit design and simulation
  • Post-silicon validation and debug
• Collaborate closely with cross-functional teams includingRF, digital, and system teams
• Stay up to date onindustry trends, competitor products, and emerging MSIP technologiesusing publicly available information
• Providetechnical leadership, including mentoring junior engineers and managing small project teams (where applicable)

Required Technical Expertise

Strong experience in one or more of the following areas:

• High-speed / high-performance MSIPs, such as:
  • ADCs (≥320 MHz bandwidth)
  • DACs
  • PLLs

Tools & Skills

• Proficiency inCadence ADE, Virtuoso XL, Spectreand other analog design flows
• Working knowledge ofMATLAB,Verilog / Verilog-AMS, and related tools
• Experience withhigh-speed interfacesbetween MSIP and digital subsystems
• Strong debugging and silicon validation experience

Preferred Qualifications

• Experience withhigh sampling rate SAR ADCs
• Prior experience inleading small teams and managing multiple projects
• Exposure toadvanced technology nodesand multi-domain integration (RF, analog, digital)

What We Value

• Strong analytical and problem-solving skills
• Ownership and end-to-end accountability
• Collaborative mindset across global teams
• Ability to balanceperformance, power, and cost trade-offsin complex systems

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