Hardware System Design Engineer – Senior or Staff - ASICS Engineering

Company:

Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

Hardware System Design Engineer, Senior Staff

Location: San Diego, CA (100% On-Site) Employment Type: Full-Time

Level: Senior or Staff — final level and title will be determined based on the selected candidate’s experience and demonstrated scope of impact.

You will be part of a hardware design team that builds high-performance FPGA-based emulation platforms. You will own the board design process — schematic capture, PCB stack-up, PCB layout, power and signal integrity simulation, BOM management, and design verification testing — while driving system-level architecture in close partnership with customers and software/firmware teams. You will work cross-functionally to evaluate design trade-offs, direct lab technicians through system installation and debug, and partner with design, CAD, and manufacturing teams on prototyping, testing, and production support. Candidates with broader scope and a track record of technical leadership may be considered at the Staff level, where they will additionally define system architecture across multiple boards/platforms, set design methodology and standards for the team, serve as the primary technical interface with customers, and mentor senior and junior engineers.

• Own the board design lifecycle: schematic capture, PCB stack-up (26+ layers), PCB layout, BOM management, and design verification testing.
• Drive system-level architecture in collaboration with customers, software, and firmware development teams.
• Perform power and signal integrity simulations for 10 Gbps+ SERDES and high-speed I/O, from model extraction through simulation, reporting, and recommended design changes.
• Lead or support FPGA board design (Xilinx and/or Altera), including DDR3/DDR4/DDR5 discrete memory subsystems.
• Direct lab technicians on system installation, bring-up, and debug of boards and multi-board systems, including root-cause investigation of the most complex issues.
• Collaborate with mechanical, PCB layout, and manufacturing teams to ensure designs are optimized for signal integrity, manufacturability (DFM), and reliability.
• Author and maintain design documentation (HDDs, pinout tables, design review packages) to support cross-team alignment and program reviews.
• Serve as a key or primary technical point of contact with customers and cross-functional stakeholders on system architecture decisions and trade-offs.
• Support factory/production builds and new product introduction (NPI) activities as needed.

• Experience with the board design process including schematic capture, PCB stack-up, PCB layout (26+ layers), BOM management, and design verification testing.
• Experience with FPGA board design (Xilinx and/or Altera).
• FPGA HDL coding experience.
• Experience with 10 Gbps or higher SERDES board designs.
• Experience performing power and signal integrity simulations for 10 Gbps+ signals, including various I/O analyses, using established methodologies from model extraction through simulation, reporting, and recommending design changes to address failing simulations.
• Experience with circuit and layout guidelines, high-speed design concepts, signal integrity, and transmission line theory.
• Experience with DDR3/DDR4/DDR5 discrete component board designs.
• System architecture design experience; candidates for the Staff level should have experience defining architecture across multiple boards/platforms.

Protocols, Tools & Test Equipment

• Familiarity with I2C, JTAG, UART, SPI, SD Card, PCIe, and eMMC protocols.
• Familiarity with test equipment including oscilloscopes, logic analyzers, and protocol analyzers.
• Board- and system-level bring-up and debug experience.
• Basic Linux/Unix experience.
• Familiarity with Microsoft Office, Mentor Graphics DxDesigner/Expedition, Vivado, Quartus, HyperLynx, Sigrity PowerSI/PowerDC, ADS, Ansys HFSS, and SPICE.

Collaboration & Professional Skills

• Proven ability to work with cross-functional teams (mechanical, PCB layout, manufacturing, software/firmware, program management) to deliver high-quality boards and systems on schedule.
• Strong written and verbal communication skills, including the ability to present design trade-offs and simulation results to technical, customer, and cross-functional audiences.
• Demonstrated ability to work independently, prioritize competing priorities, and drive tasks to closure with minimal supervision.
• Experience mentoring or providing technical guidance to junior engineers; Staff-level candidates should also demonstrate experience mentoring senior engineers and leading design reviews.

• Power supply design experience.
• Experience with signal integrity and PDN (power delivery network) simulations.
• Experience with Design for Manufacturing (DFM) and Design for Test (DFT) reviews with PCB fabricators and contract manufacturers.
• Familiarity with scripting languages (Python, Perl) for design automation, data extraction, or test/analysis workflows.
• Industry certification such as IPC Certified Interconnect Designer (CID) or equivalent.
• Experience supporting a product from concept through production release and factory NPI.
• (Staff) Experience defining board/system design methodology or reusable IP/standards adopted across multiple programs, and/or prior experience as a technical lead or architect on a hardware program.

• 5+ years’ experience in system architecture, hardware board design, and signal integrity simulations required; 10+ years typically expected for consideration at the Staff level.
• Bachelor’s or Master’s Degree in Electrical/Electronics Engineering, Computer Engineering, or a related field — or equivalent practical experience.

• This is a 100% on-site position based in San Diego, CA; the role requires regular in-person lab access to support system installation, bring-up, and debug, and is not eligible for remote or hybrid work.
• Ability to lift/move lab equipment and boards as needed, and to work in a lab environment for extended periods during bring-up and debug cycles.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field.

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Pay range and Other Compensation & Benefits:

$121,800.00 - $182,600.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm.  We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus).  In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.

If you would like more information about this role, please contact Qualcomm Careers.