Graphics Front-End Integration Engineer

Summary

Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient GPU! You’ll ensure Apple products and services can seamlessly and expertly handle the tasks that make them beloved by millions. Joining this group means you’ll be crafting and building the technology that fuels Apple’s devices. Together, we enable our customers to do all the things they love with their devices. As a member of GPU FE Design integration team, you will create GPU RTL by integrating various IPs following architectural parameters, physical constraints, DFT logic and power intent.

Minimum Qualifications

BS + 3 years of relevant experience. Experience with Verilog/System Verilog. Experience with the one of the following scripting languages: Perl/Ruby/Python.

Preferred Qualifications

Knowledge of PPA optimization techniques and implementation flows. Experience with scalable designs, DFT insertion, LEC, Lint and codeline management. Ability to debug and solve various design integration issues in a timely manner. Proficiency in logic design principles. Proficiency in programming techniques. Experience with RTL analysis and/or PPA optimization using Invio, LEC and Genus. Familiarity with GPU/CPU/SIMD Architecture and micro-architecture. Ability to solve complex problems across multiple technical domains. Ability to work well in a team and be productive under aggressive schedules.

Description

As a GPU Design Integration Engineer, you will be responsible for: - RTL integration, partitioning, design analysis, qualification, packaging and delivery. - Run logic equivalence checking between designs. - Ensure implementation readiness with RTL lint, custom checks and unit level synthesis. - Develop innovative methods to improve front-end design integration process. - Understand and contribute to specifications for design units. - Collaborate effectively with Architecture, IP, DV, SOC, DFT, IMPL teams spanning multiple sites.