Next-Gen – High-Speed Memory Subsystem ASIC Digital Design Engineer - ASICS Engineering

At Qualcomm, we believe in the power of technology. For decades, our innovations have transformed entire industries, improved billions of lives, and addressed many of society’s biggest challenges. With the world becoming increasingly connected, we have a tremendous opportunity to shape a better future. As an R&D engine that has revolutionized the way people connect, our approach to innovation is strategic and purposeful. We understand that the success of our business is fundamentally connected to the well-being of our world.

Our Team:

Our mission is to ship the very best System-On-A-Chip products in the world, putting Qualcomm in a position of leadership, in all its businesses. We are looking for hardware micro-architects and RTL designers to develop SOC Interconnects, Cache and Memory Controllers for Qualcomm Snapdragon platforms across the best of the smartphones, the performance of Windows PCs and Chromebooks, virtual reality and augmented reality devices, and automotive solutions.

What you will be doing :

• Micro-architect, design and validate RTL for blocks and modules of SOC Interconnects, Interconnect Caches and memory subsystems, and power and system level design
• Identify advanced ways to optimize hardware design for better performance, power, and cost
• Evaluate the hardware feasibilities of complex algorithms and requirements
• Develop micro architecture and specification of the new generation design
• Develop RTL for the corresponding micro architecture
• Provide essential verification and debugging activities for the corresponding design throughout the entire project cycles
• Optimize the silicon cost and improve clock speed 
• Troubleshoot silicon issues with products relevant to the corresponding design

Key-qualifications:

• The team is looking for candidates with 3+ years of experience.
• Experience or course work in Verilog/SystemVerilog design, Synopsys synthesis, low power design, test plan development, coverage-based design verification
• Experience or course work in Computer Architecture, Computer Arithmetic, Low power design, C/C++/Python programming languages is desired.
• Experience or course work in designing RTL for CPU, cache controller blocks in ASIC is a plus!
• Good communication skill and desire to work as a team player

Qualifications:

*    Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field with a GPA > 3.5 OR
*  Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field with a GPA > 3.5 OR
* PhD in Computer Engineering, Computer Science, Electrical Engineering, or related field

• Prior experience in ASIC Design and DV is a plus.