Cadence Design Systems

Develops EDA software, IP, verification tools

Lead Design Engineer – UCIe Verification

Hardware Validation & TestingConfirmed live in the last 24 hours

Full-timeBengaluru, Karnataka, IndiaNo salary listedIn-person

About the Job

Requirements

A BE, BTech, ME, MTech, or MS in Electronics, Electrical Engineering, Computer Engineering, or a related discipline.
At least 5 years of relevant design verification experience, including hands-on ownership of IP- or subsystem-level verification.
Strong expertise in SystemVerilog and UVM, constrained-random verification, functional coverage, code coverage, assertions and SVA, regression, and failure debugging.
Experience developing reusable UVM testbench components and verification infrastructure.
Strong understanding of verification methodology, test planning, coverage closure, and sign-off.
Experience with industry-standard simulators and debug environments such as Cadence Xcelium or equivalent.
Ability to analyze complex specifications and translate requirements into effective verification scenarios.
Strong debugging and problem-solving skills.

Responsibilities

Contribute to verification of complex UCIe Controller IP for chiplet and die-to-die interconnect solutions.
Work with design, architecture, validation, and cross-functional teams to develop scalable verification environments.
Validate complex protocol scenarios, drive coverage closure, debug failures, and contribute to high-quality IP releases.

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Job Description: Lead Design Engineer – UCIe Verification

Location: Bangalore, India
Function: Design Verification
Role: Lead Design Engineer – UCIe Controller Verification

Role Overview

We are looking for a highly motivated and technically strong Lead Design Engineer – Verification to join our UCIe verification team in Bangalore.

The candidate will contribute to the verification of complex UCIe Controller IP, working on next-generation chiplet and die-to-die interconnect solutions. The role requires strong hands-on expertise in SystemVerilog/UVM, verification architecture, coverage-driven verification, protocol verification, and debug.

The engineer will work closely with design, architecture, validation, and other cross-functional teams to develop scalable verification environments, validate complex protocol scenarios, drive coverage closure, debug failures, and contribute toward high-quality IP releases.

Required Qualifications

BE/BTech/ME/MTech/MS in Electronics, Electrical Engineering, Computer Engineering, or a related discipline.
5+ years of relevant Design Verification experience, with strong hands-on ownership of IP or subsystem-level verification.
Strong expertise in: SystemVerilogUVMConstrained-random verificationFunctional coverageCode coverageAssertions/SVARegression and failure debug
Experience developing reusable UVM testbench components and verification infrastructure.
Strong understanding of verification methodology, test planning, coverage closure, and sign-off.
Experience with industry-standard simulators/debug environments such as Cadence Xcelium or equivalent.
Ability to analyze complex specifications and translate requirements into effective verification scenarios.
Strong debugging and problem-solving skills.

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About the Company

Cadence Design Systems

Develops EDA software, IP, verification tools

Cadence Design Systems supplies software, hardware, and IP for electronic design automation (EDA) to help customers create advanced semiconductor chips and electronic systems. Its tools handle system design, verification, digital and analog IC design, and custom flows, while IP such as Tensilica processors and DSP cores can be licensed for integration into customer products. The offerings are delivered as software licenses with maintenance and support, plus IP licensing and occasional hardware-accelerated options. The company differentiates itself with a broad, end-to-end EDA portfolio and close collaboration with industry leaders to streamline the path from concept to silicon, aiming to help customers bring sophisticated silicon and electronics to market faster with lower risk and higher productivity.

Company size: 10,001+
Company stage: IPO
Headquarters: San Jose, CA
Founded: 1988

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