Cadence Design Systems
Develops EDA software, IP, verification tools
Senior Product Marketing Manager - PCIe and CXL Controller IP
+ Bonus + Equity
About the job
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
- At least 8 years of experience in semiconductor IP, system-on-chip, hardware design, verification, systems engineering, product management, product marketing, applications engineering, or a closely related technical role.
- Strong working knowledge of PCI Express and/or Compute Express Link technologies, including controller architecture, protocol features, system-on-chip integration, performance, power, debug, compliance, and ecosystem requirements.
- Ability to quickly understand complex hardware and software solutions and communicate their value to technical and business audiences.
- Experience working directly with customers, sales teams, engineering teams, or field application teams in a semiconductor or IP business environment.
- Ability to create clear technical collateral and influence cross-functional stakeholders.
- Own roadmap input, market requirements, and product definition for PCI Express and Compute Express Link Controller IP based on customer needs, market trends, competitive analysis, standards evolution, market segmentation, and SWOT analysis.
- Define and execute competitive marketing strategies for the PCI Express and Compute Express Link Controller IP portfolio with SerDes marketing, engineering, sales, program management, and application engineering.
- Engage with lead customers and ecosystem partners to understand system-level requirements across AI and high-performance computing infrastructure, data center accelerators, storage, networking, automotive, and advanced system-on-chip and chiplet use cases.
- Translate complex technical requirements into product requirements, value propositions, competitive positioning, product briefs, presentations, white papers, web content, and sales enablement tools.
- Collaborate with engineering teams on controller portfolio planning, including protocol feature priorities, configurability, integration requirements, compliance considerations, validation readiness, and collateral needs.
- Support design-win activities by helping sales and field teams position Cadence IP against competitive alternatives, respond to RFIs and RFPs, and articulate differentiation at technical and executive levels.
- Track industry standards and ecosystem developments, including PCI-SIG, CXL Consortium, NVMe, AMBA and Arm interconnects, and related system-on-chip and platform interface trends.
- Represent and evangelize Cadence PCI Express and Compute Express Link Controller IP at customer meetings, industry events, webinars, conferences, and appropriate digital channels.
- Synthesize unstructured customer, market, and competitive data into recommendations for senior management and cross-functional stakeholders.
- Identify solutions to product, positioning, and customer-engagement challenges while operating with ownership, urgency, and cross-functional collaboration.
- MBA or Master of Science in a technical field with strong business aptitude.
- Hands-on design, architecture, verification, application engineering, or product-management experience with PCI Express, Compute Express Link, NVMe, Ethernet, SerDes, or related high-speed interface IP.
- Familiarity with PCIe Gen5, Gen6, and Gen7; CXL 2.0, 3.x, and 4.0; PIPE; IDE; TDISP; FLIT mode; ordering rules; RAS; low-power features; compliance flows; and subsystem-level integration considerations.
- Understanding of AMBA standards and related system-on-chip fabrics or interfaces, including AXI, CHI, CXS, LTI/DTI, SMMU, and GIC-related integration considerations.
- Experience with PCIe and CXL IP integration in system-on-chips, chiplets, packages, boards, or data-center platforms, including interactions among controller, PHY/SerDes, firmware, software, and system validation.
- Participation in or close familiarity with standards bodies and ecosystem initiatives such as PCI-SIG, CXL Consortium, NVMe, and OCP.
- Ability to operate independently, manage ambiguity, prioritize effectively, and drive alignment across geographically distributed teams.
- Prior customer-facing experience presenting to architects, engineering leaders, executives, sales teams, and partner organizations.
About the company
Cadence Design Systems provides software, hardware, and IP for electronic design automation (EDA) to help customers design advanced semiconductor chips and electronic systems. Its tools cover system-level design and verification, digital and analog IC design, and custom design flows, with IP offerings like Tensilica processors and DSP cores available for licensing. It differentiates itself by offering an end-to-end EDA portfolio and deep collaboration with industry leaders across implementation, verification, and IP. The goal is to help customers bring sophisticated silicon and electronics to market faster while reducing risk and improving productivity across AI, audio, video, and automotive applications.
Company Size
10,001+
Company Stage
IPO
Headquarters
San Jose, California
Founded
1988
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Simplify's Take
What believers are saying
- Q2 2026 revenue hit $1.584 billion, up 24%, with record $8.1 billion backlog.
- Cadence launched AuraStack in July 2026 and ChipStack earlier, expanding agentic AI monetization.
- Intel Foundry, Rapidus, and Positron AI validate Cadence's 2026 design-win momentum.
What critics are saying
- On July 28, 2025, Cadence accepted over $140 million export-control penalties and probation.
- China exposure remains toxic: the NUDT case ties Cadence to restricted military customers.
- AI-design startups and NVIDIA partnerships pressure Cadence's pricing power by 2027.
What makes Cadence Design Systems unique
- Cadence owns silicon-to-system EDA, IP, emulation, and PCB flows across the stack.
- On July 31, 2026, Cadence certified Intel 18A-P and 14A reference flows.
- On September 2, 2026, Cadence passed PCIe 6.0 compliance at 64 GT/s.
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Benefits
Health Insurance
Dental Insurance
Life Insurance
Flexible Work Hours
Paid Vacation
Paid Sick Leave
Growth & Insights and Company News
6 month growth
↑ 0%1 year growth
↓ -2%2 year growth
↓ -2%Cadence subsystem for PCIe 6.0 architecture achieves first-pass PCI Express specification compliance. Complete x8 subsystem solution in TSMC N3 process demonstrates industry readiness for mass production and de-risks adoption for AI/HPC customers. Cadence (Nasdaq: CDNS) today announced that its PHY and controller IP for the PCI Express(R)(PCIe(R) 6.0 specification, implemented in the TSMC N3 process, achieved first-pass success at the recent PCI-SIG(R) compliance workshop held in late July. The workshop marked the industry's first official event for PCIe 6.0 specification compliance testing, with Cadence's x8 subsystem solution tested at the full PCIe 6.0 specification speed of 64 GT/s. The complete Cadence subsystem solution, comprising both PHY and controller, successfully passed all official PCIe 6.0 compliance specification tests and is on PCI-SIG's Integrators List. "PCI Express is a crucial scale-up interconnect for AI/HPC data centers and AI factories, and Cadence's subsystem for the PCIe 6.0 specification delivers best-in-class performance with among the lowest power in the industry," said Marc Loinaz, vice president of research and development for high-performance PHY, Silicon Solutions Group at Cadence. "This first-pass compliance success validates our complete PHY and controller solution and gives customers confidence that our technology is fully interoperable and ready for production." The milestone underscores the importance of early ecosystem collaboration in bringing new standards to market. Cadence worked closely with PCI-SIG, test equipment providers, and industry partners in the months leading up to the official compliance workshop, conducting interoperability testing to identify and resolve potential issues before the formal evaluation. "As PCIe 6.0 technology enables the next wave of AI and high-performance computing systems, rigorous compliance and interoperability testing are essential for ecosystem success," said Brig Asay, General Manager, Network Data Center, Keysight Technologies. "Cadence's first-pass compliance achievement reflects both the quality of its PCIe 6.0 subsystem implementation and the effectiveness of comprehensive validation using Keysight's test and measurement solutions. We are pleased to support industry leaders in accelerating PCIe 6.0 technology deployment with confidence." "Cadence is a long-standing PCI-SIG member helping to further PCIe technology adoption," said Al Yanes, president and chairperson of PCI-SIG. "Cadence's PCIe 6.0 compliance milestone plays a role in the continued advancement of PCIe technology architecture." PCIe 6.0 technology addresses growing demand for high-bandwidth connectivity in AI and high-performance computing systems, where the standard is used for accelerator cards, network interfaces, and storage devices. The interface is expected to see wide adoption in data center and AI infrastructure, with broader deployment in automotive and enterprise systems following as the ecosystem matures. "Positron AI has licensed Cadence's SerDes IP for the PCIe 6.0 specification for our AI inference accelerator chip," said Thomas Sohmers, CTO at Positron AI. "Cadence's complete PCIe 6.0 subsystem built in silicon and robust interoperability testing give us confidence that our PCIe 6.0 interface will meet the high-bandwidth connectivity demands of our transformer workloads." Key features of Cadence's PCIe 6.0 technology solution include: * Complete subsystem solution with PHY and controller built in silicon * ADC and DSP-based equalization * Firmware-optimized SerDes operation * Multi-protocol flexibility and support * Optimized for low power, including support for the latest PCI-SIG engineering change notices (ECNs) * Certification for x8 configuration on TSMC N3 process PCI-SIG has continued to advance the PCIe standard to meet the needs of advanced HPC and AI workloads. Cadence offers a broad portfolio of PCIe technology solutions up to the PCIe 7.0 specification. Cadence's complete subsystem solution for PCIe 6.0 technology, including PHY and controller, is available now for SoC providers to design in. For more information on Cadence IP for PCIe 6.0 technology, visit the Cadence PCIe 6.0 and CXL PHY product page or download the Design IP brochure.
Cadence has announced a collaboration with Analog Devices to develop the latest generation of SHARC automotive audio processors. The partnership integrates Cadence's Tensilica DSP architecture into ADI's ADSP product family, enabling enhanced audio experiences and AI capabilities for automotive platforms. ADI is introducing the ADSP-SC84x/2184x platform, featuring the new SHARC-FX processor core developed jointly with Cadence. Built on 16nm process technology, the platform delivers five times higher performance compared to the previous generation. The SHARC-FX core supports AI-driven audio processing, including noise cancellation and voice assistance. The processors power various automotive applications, including advanced driver alerts, road noise cancellation, immersive 3D audio, and voice processing. The architecture enables on-chip AI workloads whilst maintaining real-time performance for safety-critical automotive systems.
Nilsine Partners LLC purchased a new position in shares of Cadence Design Systems, Inc. (NASDAQ:CDNS – Free Report) during the 2nd quarter, according to the company in its most recent filing with the Securities and Exchange Commission. The firm purchased 9,186 shares of the software maker’s stock, valued at approximately $3,448,000. A number of other […]
Cadence announced its PHY and controller IP for PCI Express 6.0, implemented in TSMC's N3 process, achieved first-pass success at the recent PCI-SIG compliance workshop in late July. The workshop marked the industry's first official event for PCIe 6.0 specification compliance testing. Cadence's x8 subsystem solution was tested at the full PCIe 6.0 specification speed of 64 GT/s. The complete subsystem, comprising both PHY and controller, successfully passed all official PCIe 6.0 compliance specification tests and is now on PCI-SIG's Integrators List. PCIe 6.0 technology addresses growing demand for high-bandwidth connectivity in AI and high-performance computing systems. The interface is expected to see wide adoption in data centre and AI infrastructure. Cadence's complete subsystem solution for PCIe 6.0 technology is available now for SoC providers.
Jim Cramer defended Cadence Design Systems on Mad Money, arguing the stock's underperformance stems from misplaced fears about AI disruption. Despite being down over 10% in 12 months, Cramer said Cadence's chip design software is indispensable and that AI is actually a tailwind for the company. Cadence reported second-quarter revenue of $1.58 billion, up 24.2% year-over-year, with earnings per share of $2.11 beating expectations. Total backlog reached a record $8.1 billion. IP revenue surged over 40%, supported by partnerships with Intel and Samsung. Management raised its full-year 2026 revenue guidance to between $6.26 billion and $6.34 billion, with earnings per share projected at $8.05 to $8.15. Cramer attributed the stock's struggles to market fears that AI tools from companies like Anthropic or OpenAI could replace Cadence's software.