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Marvell

High-performance semiconductor solutions for data infrastructure

Analog Layout Principal Engineer

Silicon & ASIC DesignConfirmed live in the last 24 hours
Full-timeBengaluru, Karnataka, IndiaIn-person

About the Job

Requirements

  • A bachelor's or master's degree (BE/B.Tech or MS/M.Tech) in Electronics & Communication, Electrical & Electronics, or a related field from a reputed institution is required.
  • At least 15 years of experience in high-speed analog, mixed-signal, and custom layout design is required.
  • Broad exposure across multiple projects, technology nodes, and layout architectures is required.
  • A deep understanding of electrical engineering fundamentals and layout behavior across advanced nodes is required.
  • Proven experience handling complex and critical IPs with end-to-end ownership is required.
  • Expert-level proficiency in EDA tools, with the ability to influence layout flows and methodologies, is required.
  • Demonstrated ability to introduce innovative and optimized layout solutions for complex designs is required.
  • A strong track record of delivering high-speed and/or precision analog layouts across multiple process technologies is required.
  • Expertise in device matching, signal flow optimization, clock routing, shielding, parasitic minimization, biasing, and robust power routing is required.
  • A solid understanding of reliability considerations, including EM/IR, latch-up prevention, ESD protection, and power planning, is required.
  • The ability to present to global teams and engage stakeholders across organizational levels is required.

Responsibilities

  • Design and develop complex analog, mixed-signal, and custom layouts independently using Cadence Virtuoso and similar EDA tools across advanced nodes, including deep sub-micron, FinFET, and GAA.
  • Drive end-to-end physical verification closure by resolving DRC, LVS, ERC, and antenna violations within project timelines.
  • Drive layout architecture, shielding, isolation, EM/IR optimization, and parasitic management.
  • Own layout planning from floor planning through final tapeout.
  • Coordinate with design, verification, package, and physical implementation teams to execute projects successfully.
  • Support tapeout activities and resolve critical design issues under aggressive schedules.
  • Lead technical discussions and layout reviews, and contribute to knowledge sharing and process improvement initiatives.
  • Serve as the technical focal point for domain expertise within the team.
  • Own the cluster, including high-level integration and top-level layout decisions.
  • Provide critical layout feedback that influences circuit quality, performance, and architecture.
  • Apply engineering judgment to select optimal layout techniques across projects.
  • Represent the layout team in cross-functional discussions and decision-making forums.
  • Lead large teams or coordinate multiple macro owners to drive project convergence.
  • Act as the key interface between layout and design teams to ensure clear communication and alignment.
  • Stay updated with evolving semiconductor technologies, tools, and methodologies.

About the Company

Marvell

High-performance semiconductor solutions for data infrastructure

Marvell Technology, Inc. creates high-performance semiconductor products that power data infrastructure for telecommunications operators, data centers, and enterprises. Its offerings span computing, storage, and networking to enable efficient, secure data transmission, storage, and processing. The products are programmable and scalable platforms designed for high bandwidth and strong security, supporting 5G networks and the broader digital economy. Revenue comes from designing, manufacturing, licensing, and providing related services to other businesses that integrate these components into their own products. Unlike many peers, Marvell emphasizes programmable, scalable platforms tailored to data infrastructure needs and long-term partnerships with enterprise and telecom customers. The company aims to help customers upgrade their networks and data systems to increase capacity, performance, and efficiency while expanding its own business in the data infrastructure space.

Company size
10,001+
Company stage
IPO
Headquarters
Santa Clara, CA
Founded
1995

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