ESD Engineer

Summary

At Apple, we work every single day to craft products that enrich people’s lives. In this highly visible role, you will take ownership of the ESD and Latch-Up requirements of all ICs developed by and for Apple. Your mission is to ensure the silicon is designed to meet Apple's ESD specifications and manufacturing requirements. The role involves working closely with our diverse teams within Apple as well as external vendors. Occasional travel might be required. Do you love working on challenges that no one has solved yet? Are you excited to build Apple’s products that strive for the highest expectations of quality, innovation and efficiency? We have an opportunity for an especially innovative ESD Designer with strong fundamentals! We are looking forward to having you join our fast growing team and help us deliver on these challenges while enjoying an amazing culture where you lead your career!

Minimum Qualifications

BS degree in technical discipline with years of relevant experience.

Preferred Qualifications

MS degree, preferred Deep understanding of transistor device characteristics Solid understanding of models used for testing ESD, including HBM, CDM, MM and IEC-61000-4-2 Knowledge of state-of-the-art ESD circuit design techniques and topologies Hands-on experience with design/layout EDA tools, including Virtuoso, Calibre, Allegro, etc. Experience with ESD/LUP test and characterization equipment Strong initiative, collaboration, and ownership of responsibilities, productive, able to meet challenging deadlines Excellent written and verbal communication skills

Description

Work in a cross-functional team that delivers high quality on-chip IPs immune to ESD/EOS and latchup events. Ensure ESD robust designs with minimum cost to mission-mode functions.

Responsibilities

Define the ESD methodology for all silicon developed by Apple and to specify the chip and IP level ESD requirements. Design ESD protection devices and circuits to meet design requirements -Develop test structures to characterize Si for ESD/LUP properties. Drive ESD/LUP related debug activities.