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Cadence Design Systems

Develops EDA software, IP, verification tools

ATE Test Engineering Architect

Engineering ManagementConfirmed live in the last 24 hours
Full-timeSan Jose, CA, USAIn-person

About the Job

Requirements

  • A Bachelor of Science degree with at least 12 years of experience, a Master of Science degree with at least 10 years of experience, or a Doctor of Philosophy degree with at least 8 years of experience.
  • Hands-on experience with CP/FT test program development.
  • Experience with the Advantest 93K automated test equipment platform.
  • A solid understanding of design-for-test and silicon debug.
  • Proven experience supporting production and working with offshore test partners.
  • Strong problem-solving and cross-functional communication skills.

Responsibilities

  • Lead automated test equipment development for wafer sort and final test.
  • Drive first-silicon bring-up, debug, and characterization.
  • Define test coverage, binning, guard-banding, and production release criteria.
  • Analyze yield and failure data and drive test-related yield and quality improvements.
  • Partner with design-for-test, design, outsourced semiconductor assembly and test providers, and test houses to ensure manufacturable solutions.
  • Support qualification, production ramp, and sustained manufacturing.
  • Mentor engineers and act as a technical test leader across product teams.

About the Company

Cadence Design Systems

Develops EDA software, IP, verification tools

Cadence Design Systems supplies software, hardware, and IP for electronic design automation (EDA) to help customers create advanced semiconductor chips and electronic systems. Its tools handle system design, verification, digital and analog IC design, and custom flows, while IP such as Tensilica processors and DSP cores can be licensed for integration into customer products. The offerings are delivered as software licenses with maintenance and support, plus IP licensing and occasional hardware-accelerated options. The company differentiates itself with a broad, end-to-end EDA portfolio and close collaboration with industry leaders to streamline the path from concept to silicon, aiming to help customers bring sophisticated silicon and electronics to market faster with lower risk and higher productivity.

Company size
10,001+
Company stage
IPO
Headquarters
San Jose, CA
Founded
1988

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